Patents by Inventor Guangbing Chen

Guangbing Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210305943
    Abstract: Provided in the present invention is a transconductance amplifier based on a self-biased cascode structure. The transconductance amplifier includes a self-biased cascode input-stage structure constituted by PMOS (P-channel Metal Oxide Semiconductor) input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by NMOS (N-channel Metal Oxide Semiconductor) transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor Cc, an amplifier load capacitor CL, a reference current source Iref and a PMOS transistor MO that provides a constant current source function. Further provided in the present invention is a transconductance amplifier based on a self-biased cascode structure, which adopts an NMOS transistor as an input transistor.
    Type: Application
    Filed: January 26, 2016
    Publication date: September 30, 2021
    Inventors: DAIGUO XU, GANGYI HU, RUZHANG LI, JIAN'AN WANG, GUANGBING CHEN, YUXIN WANG, TAO LIU, LU LIU, MINMING DENG, HANFU SHI, XU WANG
  • Publication number: 20210297080
    Abstract: The present disclosure provides a low-jitter frequency division clock circuit, including: a clock control signal generation circuit, to generate clock signals having different phases; a low-level narrow pulse width clock control signal generation circuit, to generate a low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, to generate a high-level narrow pulse width clock control signal; and a frequency division clock generation circuit, to generate a frequency division clock signal according to low-level narrow pulse width clock control signal and high-level narrow pulse width clock control signal. The delay from a clock input end to an output end of low-jitter frequency division clock circuit is up to three logic gates.
    Type: Application
    Filed: December 13, 2018
    Publication date: September 23, 2021
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Tao LIU, Jian'an WANG, Yuxin WANG, Guangbing CHEN, Dongbing FU, Ruzhang LI, Shengdong HU, Zhengping ZHANG, Jun LUO, Daiguo XU, Minming DENG, Yan WANG
  • Patent number: 11121677
    Abstract: Provided in the present invention is a transconductance amplifier based on a self-biased cascode structure. The transconductance amplifier includes a self-biased cascode input-stage structure constituted by PMOS (P-channel Metal Oxide Semiconductor) input transistors M1, M2, M3 and M4, a self-biased cascode first-stage load structure constituted by NMOS (N-channel Metal Oxide Semiconductor) transistors M5, M6, M7 and M8, a second-stage common-source amplifier structure constituted by an NMOS transistor M9 and a PMOS transistor M10, a bias circuit structure constituted by NMOS transistors M11 and M12 and a PMOS transistor M13, an amplifier compensation capacitor Cc, an amplifier load capacitor CL, a reference current source Iref and a PMOS transistor M0 that provides a constant current source function. Further provided in the present invention is a transconductance amplifier based on a self-biased cascode structure, which adopts an NMOS transistor as an input transistor.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: September 14, 2021
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE
    Inventors: Daiguo Xu, Gangyi Hu, Ruzhang Li, Jian'an Wang, Guangbing Chen, Yuxin Wang, Tao Liu, Lu Liu, Minming Deng, Hanfu Shi, Xu Wang
  • Publication number: 20210280513
    Abstract: The present disclosure provides a one-time programmable capacitive fuse bit, including an upper plate, the upper plate includes a plurality of fuses arranged side by side and spaced by an internal from each other, middle portions of two adjacent fuses are connected to each other; a connecting portion connected to the fuse is disposed above two ends and the middle portion of each of the plurality of fuses; the fuse bit further includes a lower plate corresponding to the two ends and the middle portion of the fuse, the lower plate is disposed below the fuse; the lower plate corresponding to the middle portion of the fuse is opposite to the connecting portion corresponding to the middle portion of the fuse; a hollow portion is disposed between the lower plate corresponding to the middle portion of the fuse and the lower plate corresponding to both ends of the fuse.
    Type: Application
    Filed: July 18, 2018
    Publication date: September 9, 2021
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Mingyuan XU, Shuiqin YAO, Liang Li, Xiaofeng SHEN, Hongrui YANG, Jian'an WANG, Dongbing FU, Guangbing CHEN, Xingfa HUANG, Xi CHEN
  • Publication number: 20210281269
    Abstract: The present disclosure provides a buffer circuit and a buffer. The buffer circuit includes: an input follower circuit for following the voltage change of the first input signal; an input follower linearity boosting circuit for improving follower linearity of the input follower circuit; a first voltage bootstrap circuit for bootstrapping the voltage of the first input signal; a second voltage bootstrap circuit for bootstrapping the voltage of the second input signal; a third voltage bootstrap circuit for providing corresponding quiescent operation point voltage; a compensation follower circuit for following the compensation voltage; a compensation follower linearity boosting circuit for improving follower linearity of the compensation follower circuit; a first load for collecting the buffered voltage; a bias circuit for providing a bias current for the buffer; a bias linearity boosting circuit for improving linearity of the bias circuit; a second load for generating a nonlinear compensation current.
    Type: Application
    Filed: December 13, 2018
    Publication date: September 9, 2021
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Ting LI, Gangyi HU, Ruzhang LI, Yong ZHANG, Zhengbo HUANG, Yabo NI, Xingfa HUANG, Jian'an WANG, Guangbing CHEN, Dongbing FU, Jun YUAN, Zicheng XU
  • Publication number: 20210278867
    Abstract: The present disclosure provides a differential reference voltage buffer, including: a buffer stage, including at least a first transistor and a second transistor; a control circuit, connected with the buffer stage and forming a negative feedback structure for generating a differential reference voltage; a current compensation circuit for compensating a resistive load current of the control circuit; and a drive stage for generating an output differential reference voltage. The differential reference voltage is generated according to an external input reference voltage and a common mode input voltage. The common mode voltage can be set separately, so that the flexibility is high. The current generated by a resistive network in the control circuit is compensated by the current compensation circuit, so that the current of a follow device in the buffer stage is not influenced by the control circuit, thereby generating a differential reference voltage with high accuracy output.
    Type: Application
    Filed: December 13, 2018
    Publication date: September 9, 2021
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Yan WANG, Gangyi HU, Tao LIU, Jian'an WANG, Daiguo XU, Guangbing CHEN, Dongbing FU
  • Publication number: 20210211122
    Abstract: A duty cycle adjustment apparatus comprises a first edge extraction unit for extracting a rising edge of a first clock signal; a locking discrimination unit configured to output a control signal according to a comparison result between a discrimination voltage and a stabilized voltage, and select to connect the first clock signal or the clock output signal; an integration unit, configured to convert the feedback signal into the stabilized voltage, amplify the stabilized voltage to reach a reference voltage, and output a control voltage; a charge pump, configured to output a second clock signal according to the control voltage; a second edge extraction unit, configured to extract a falling edge of the second clock signal; and a phase discriminator, configured to compare a phase of the rising edge of the first clock signal with a phase of the falling edge of the second clock signal to generate the clock output signal.
    Type: Application
    Filed: July 21, 2017
    Publication date: July 8, 2021
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Xi Chen, Liang Li, Guangbing Chen, Yuxin Wang, Dongbing Fu, Xingfa Huang, Mingyuan Xu, Xiaofeng Shen
  • Publication number: 20210135678
    Abstract: The present disclosure provides an error compensation correction system and method for an analog-to-digital converter with a time interleaving structure, the system includes an analog-to-digital converter with a time interleaving structure, a master clock module, a packet clock module, an error correction module, an adaptive processing module and an overall MUX circuit. Through the error compensation correction system and method for the analog-to-digital converter with a time interleaving structure according to the present disclosure, lower correction hardware implementation complexity and higher stability are ensured. The system and method according to the present disclosure are particularly suitable for interchannel mismatch error correction of dense channel time interleaving ADC, and the performance of the time interleaving ADC is improved.
    Type: Application
    Filed: July 25, 2018
    Publication date: May 6, 2021
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Jie PU, Gangyi HU, Jian'an WANG, Guangbing CHEN, Liang LI, Ting LI, Daiguo XU, Xingfa HUANG, Xi CHEN, Tiehu LI, Youhua WANG
  • Publication number: 20210135641
    Abstract: The present disclosure provides a clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.
    Type: Application
    Filed: July 25, 2018
    Publication date: May 6, 2021
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Xiaofeng SHEN, Xingfa HUANG, Liang LI, Xi CHEN, Mingyuan XU, Jian'an WANG, Dongbing FU, Guangbing CHEN
  • Publication number: 20210126646
    Abstract: The present disclosure provides a pipelined analog-to-digital converter having input signal pre-comparison and charge redistribution, including: one-stage or multi-stage of pipelined structure unit, a first flash analog-to-digital converter, and an adjusting output unit. Each stage of the pipelined structure unit is used to quantify the input signal. The first flash analog-to-digital converter quantizes a residual signal output by a final pipelined structure unit, and outputs a corresponding quantized value. The adjusting output unit combines each of the quantized values according to a connection order of the multi-stage pipelined structure unit and a flash analog-to-digital conversion unit to output a complete quantization result.
    Type: Application
    Filed: September 11, 2017
    Publication date: April 29, 2021
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Zhengbo HUANG, Ting LI, Yong ZHANG, Ruzhang LI, Guangbing CHEN, Yabo NI
  • Patent number: 10979066
    Abstract: The present disclosure provides a pipelined analog-to-digital converter having input signal pre-comparison and charge redistribution, including: one-stage or multi-stage of pipelined structure unit, a first flash analog-to-digital converter, and an adjusting output unit. Each stage of the pipelined structure unit is used to quantify the input signal. The first flash analog-to-digital converter quantizes a residual signal output by a final pipelined structure unit, and outputs a corresponding quantized value. The adjusting output unit combines each of the quantized values according to a connection order of the multi-stage pipelined structure unit and a flash analog-to-digital conversion unit to output a complete quantization result.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: April 13, 2021
    Assignee: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Zhengbo Huang, Ting Li, Yong Zhang, Ruzhang Li, Guangbing Chen, Yabo Ni
  • Publication number: 20210070980
    Abstract: Thermosetting resin composition, prepreg and metal foil clad laminate made therefrom. The thermosetting resin composition comprises (A): a solvent-soluble multifunctional vinyl aromatic copolymer, wherein same is a multifunctional vinyl aromatic copolymer having structural units from monomers comprising a divinyl aromatic compound (a) and ethyl vinyl aromatic compound (b); and (B), wherein same is selected from olefin resins having a number-average molecular weight of 500-10,000 and containing 10%-50% by weight of a styrene structure, and the molecules thereof contain a 1,2-addition butadiene structure.
    Type: Application
    Filed: October 19, 2017
    Publication date: March 11, 2021
    Inventors: Xianping ZENG, Chiji GUAN, Guangbing CHEN, Haosheng XU
  • Patent number: 10944390
    Abstract: The present disclosure provides a high-speed and low-noise dynamic comparator, which includes: an input unit, including an input NMOS transistor and an input PMOS transistor; a latch unit, including a latching NMOS transistor and a latching PMOS transistor, where the latching NMOS transistor and the latching PMOS transistor are connected to form a latch structure; a pull-up unit, including a pull-up PMOS transistor connected to the input NMOS transistor; and a substrate bootstrap voltage generation circuit, generating a substrate bootstrap voltage.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: March 9, 2021
    Assignee: NO. 24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Daiguo Xu, Gangyi Hu, Ruzhang Li, Jian'an Wang, Guangbing Chen, Dongbing Fu, Shiliu Xu, Tao Liu, Jie Pu, Zhihua Feng
  • Publication number: 20200412353
    Abstract: The present disclosure provides a high-speed and low-noise dynamic comparator, which includes: an input unit, including an input NMOS transistor and an input PMOS transistor; a latch unit, including a latching NMOS transistor and a latching PMOS transistor, where the latching NMOS transistor and the latching PMOS transistor are connected to form a latch structure; a pull-up unit, including a pull-up PMOS transistor connected to the input NMOS transistor; and a substrate bootstrap voltage generation circuit, generating a substrate bootstrap voltage.
    Type: Application
    Filed: July 18, 2018
    Publication date: December 31, 2020
    Applicant: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATIO
    Inventors: Daiguo XU, Gangyi HU, Ruzhang LI, Jian'an WANG, Guangbing CHEN, Dongbing FU, Shiliu XU, Tao LIU, Jie PU, Zhihua FENG
  • Patent number: 10858514
    Abstract: Copper clad laminates and a resin composition and a pre-preg and a laminate using the composition. The resin composition contains: (A) a prepolymer of vinyl thermosetting polyphenylene ether and a bifunctional maleimide or a multifunctional maleimide; and, (B) a polyolefin resin. Employing the prepolymer of vinyl thermosetting polyphenylene ether and the bifunctional maleimide or the multifunctional maleimide, solves the problem of incompatibility of the bifunctional maleimide or the multifunctional maleimide with the vinyl thermosetting polyphenylene ether and the polyolefin resin. An aqueous glue solution so mixed is uniform and consistent, the prepreg has a uniform expression, and a substrate resin area is free of a phase-separation problem.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: December 8, 2020
    Assignee: Shengyi Technology Co., Ltd.
    Inventors: Xianping Zeng, Guangbing Chen, Chiji Guan, Wenhua Yang
  • Patent number: 10778092
    Abstract: The present disclosure provides a negative voltage generating circuit having an automatic voltage adjustment function, including a negative voltage generating circuit and a feedback control module. The negative voltage generated by the negative voltage generating circuit is adjusted by the feedback control module. The negative voltage generating circuit having the automatic voltage adjustment function of the present disclosure can automatically adjust the charge current of the charge pump according to the load current, thereby realizing the stability of the output voltage, such that the traditional analog circuit structure can work normally under the extremely low power supply voltage, and is particularly suitable for the deep submicron process. The present disclosure also realizes the digital adjustment of the output voltage, the negative voltage output is no longer single, and can be adjusted according to actual needs.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: September 15, 2020
    Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Rongbin Hu, Yonglu Wang, Zhengping Zhang, Jian'an Wang, Guangbing Chen, Dongbing Fu, Yuxin Wang, Hequan Jiang, Gangyi Hu
  • Patent number: 10745599
    Abstract: The present invention relates to a polyphenyl ether resin composition and a use thereof in a high-frequency circuit substrate. The polyphenyl ether resin composition comprises a vinyl-modified polyphenyl ether resin and an organic silicon resin containing unsaturated double bonds and having a three-dimensional net structure. The high-frequency circuit substrate of the present invention has a high glass-transition temperature, a high thermal decomposition temperature, a high interlayer adhesive force, a low dielectric constant and a low dielectric loss tangent, and is very suitable as a circuit substrate of high-speed electronic equipment.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: August 18, 2020
    Assignee: Shengyi Technology Co., Ltd.
    Inventors: Guangbing Chen, Xianping Zeng, Chiji Guan
  • Patent number: 10735018
    Abstract: Disclosed is a successive approximation algorithm-based ADC self-correcting circuit, comprising: a coding circuit, a voltage dividing resistor string, a comparator array, a multi-path selection switch, a first digital-to-analog converter, a reference circuit, a control register, and a data register; an input end of the coding circuit is connected to an output end of the comparator array; a positive-phase input end of each comparator in the comparator array is connected to a mobile end of the multi-path selection switch; a negative-phase input end of each comparator in the comparator array is correspondingly connected between each two neighboring resistors in the voltage dividing resistor string; an enabling end of the comparator array is connected to the control register; a first immobile end of the multi-path selection switch is used for receiving an analog signal, a second immobile send is connected to an output end of the first digital-to-analog converter, and a control end is connected to the control regi
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: August 4, 2020
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE
    Inventors: Rongbin Hu, Yonglu Wang, Zhengping Zhang, Jian'an Wang, Guangbing Chen, Dongbing Fu, Yuxin Wang, Hequan Jiang, Gangyi Hu
  • Publication number: 20200195270
    Abstract: Disclosed is a successive approximation algorithm-based ADC self-correcting circuit, comprising: a coding circuit, a voltage dividing resistor string, a comparator array, a multi-path selection switch, a first digital-to-analog converter, a reference circuit, a control register, and a data register; an input end of the coding circuit is connected to an output end of the comparator array; a positive-phase input end of each comparator in the comparator array is connected to a mobile end of the multi-path selection switch; a negative-phase input end of each comparator in the comparator array is correspondingly connected between each two neighboring resistors in the voltage dividing resistor string; an enabling end of the comparator array is connected to the control register; a first immobile end of the multi-path selection switch is used for receiving an analog signal, a second immobile send is connected to an output end of the first digital-to-analog converter, and a control end is connected to the control regi
    Type: Application
    Filed: June 21, 2017
    Publication date: June 18, 2020
    Inventors: RONGBIN HU, YONGLU WANG, ZHENGPING ZHANG, JIAN'AN WANG, GUANGBING CHEN, DONGBING FU, YUXIN WANG, HEQUAN JIANG, GANGYI HU
  • Publication number: 20200157332
    Abstract: A thermosetting resin composition and a prepreg and a metal foil-covered laminate made using same, the thermosetting resin composition comprising component (A): a solvent-soluble polyfunctional vinyl aromatic copolymer, the copolymer being a poly-functional vinyl aromatic copolymer having a stoctoal unit derived from monomers comprising divinyl aromatic compound (a) and ethyl vinyl aromatic compound (b); and component (B): a vinyl-containing organic silicone resin. The prepreg and metal foil-covered laminate made from the thermosetting resin composition have good toughness, and maintain a high glass transition temperature, a low water absorption, dielectric properties and humidity resistance, being suitable for the field of high-frequency and high-speed printed circuit boards and the processing of multilayer printed circuit boards.
    Type: Application
    Filed: October 19, 2017
    Publication date: May 21, 2020
    Inventors: Chiji GUAN, Xianping ZENG, Guangbing CHEN, Haosheng XU