Abstract: A comparator based on a pre-amplifier stage structure and an analog-to-digital converter are provided. The comparator includes: a first pre-amplifier stage, where an input terminal of the first pre-amplifier stage is connected to a differential input signal, to amplify and output the differential input signal so as to output a first differential output signal; a second pre-amplifier stage, where an input terminal of the second pre-amplifier stage is connected to the first differential output signal, to amplify and output the first differential output signal so as to output a second differential output signal, and a positive feedback unit is disposed between an output terminal of the second pre-amplifier stage and the input terminal of the second pre-amplifier stage, to increase a voltage gain of the second pre-amplifier stage by using the positive feedback unit; and a latch, an input terminal thereof connected to the second differential output signal.

Abstract: Reference voltage circuits and methods for designing the same are provided. The reference voltage circuit includes: a reference core unit configured to output a reference voltage; a main amplification unit connected to the reference core unit and configured to form feedback to the reference core unit; and a feedforward amplification unit connected to the main amplification unit and configured to form feedforward to the main amplification unit. The reference core unit, the main amplification unit, and the feedforward amplification unit form a third-order negative feedback loop to improve a power supply rejection ratio of the reference voltage.

Abstract: An adaptive current generation circuit includes an inverter drive chain, a frequency divider, a frequency detector, a low-pass filter, a static comparator group, and a controllable current mirror. An input analog signal of the input buffer is converted into a frequency discrimination voltage in a direct current form sequentially through conversion of the inverter drive chain, frequency division of the frequency divider, frequency detection of the frequency detector, and conversion of the low-pass filter. Then the static comparator group performs a plurality of times of comparison to obtain N bits of digital codes. Finally, the controllable current mirror is controlled by using the N bits of digital codes. The controllable current mirror provides a magnitude-adjustable input current for the input buffer under control of the N bits of digital codes. A magnitude of the input current is positively correlated with a frequency of the input analog signal.

Abstract: A comparator circuit includes: a first pre-amplification stage, which amplifies an input signal in the comparison state to generate a first output signal; a second pre-amplification stage, which switches between a reset state and a comparison state according to the first output signal, amplifies the first output signal in the comparison state to generate a second output signal, and provides positive feedback for the second output signal through a first positive feedback structure; and a latch stage, which, in the reset state, resets an output terminal of the latch stage to a second preset level according to the clock signal, and in the comparison state, controls a second positive feedback structure and a third positive feedback structure to be enabled through the second output signal and the clock signal to provide positive feedback to the output terminal.

Abstract: A comparison method includes: providing a successive approximation register analog-to-digital converter, where the successive approximation register analog-to-digital converter includes n?1 weighted capacitors, a charge transfer capacitor, and a comparator; sampling an differential input signal by using the first weighted capacitor and the charge transfer capacitor; importing the differential input signal stored on the charge transfer capacitor, where the differential input signal is transferred and redistributed on the charge transfer capacitor and n?2 other weighted capacitors than the first weighted capacitor, and completing the first time of comparison; and importing the differential input signal stored on the first weighted capacitor and the differential input signal stored on the charge transfer capacitor, importing a reference voltage by using the second to jth weighted capacitors, where the differential input signal and the reference voltage are transferred and redistributed on a capacitor array, and

Abstract: A circuit for channel randomization based on time-interleaved ADC includes: a channel selection module for outputting M clock reception control signals and encoded N data reception control signals based on a main clock and a generated random number; a multi-phase clock distribution module for generating N multi-phase clocks according to a sampling main clock, redistributing the multi-phase clocks according to the clock reception control signals, and outputting M redistributed clock signals; a time-interleaved ADC module for outputting M output data and a corresponding number of channel quantization completion signals according to the redistributed clock signals; an adjustable delay module for setting a delay length for the data reception control signals; and a timing distribution control module for controlling, according to delayed data reception control signals and the channel quantization completion signals, the output data to be output sequentially in chronological order.

Abstract: A device for encoding pipeline ADC includes: a comparator circuit connected to differential input signals and outputting a plurality of comparison results; a first encoding circuit, performing a pairwise NAND operation on the plurality of comparison results to output a plurality of NAND operation results, and outputting a first signal or/and a second signal based on the plurality of NAND operation results and the level of a first selection signal under the control of a clock signal; an encoding control circuit, generating a second selection signal based on the occurrence probability of each signal in a first digital code, receiving a third signal and a fourth signal and outputting a first selection signal according to the level of the second selection signal; a second encoding circuit, outputting a second digital code according to the first digital code under the control of switching of a plurality of switching transistors.

Abstract: A method for correcting an analog-to-digital converter includes the following steps: extracting gain errors and weight errors of all conversion stages of an analog-to-digital converter; performing first correction on the analog-to-digital converter based on the gain errors and the weight errors; extracting jitter errors of all conversion stages of the analog-to-digital converter after the first correction; and performing a second correction on the analog-to-digital converter based on the jitter errors. According to the disclosure, the gain errors, the weight errors, and the jitter errors of all conversion stages are successively extracted, and then the analog-to-digital converter is corrected. Precision after the corrections is higher.

Abstract: A method for calibrating an analog-to-digital converter includes the following steps: conducting an initial performance test and judgement on the analog-to-digital converter; if the initial performance test succeeds, performing a pre-trimming and judgement on the analog-to-digital converter; if the pre-trimming succeeds, performing an error extraction on the analog-to-digital converter, obtaining errors of conversion stages of the analog-to-digital converter; performing an error soft trimming and test on the analog-to-digital converter according to the errors of the conversion stages; and if the error soft trimming and test of the analog-to-digital converter succeed, performing an error hard trimming and test on the analog-to-digital converter according to the errors of the conversion stages.

Abstract: The present application provides a circuit and a method for sampling an imaging signal, the circuit includes: a first sampling module sampling the imaging signal N times under the control of N first sampling signals and a second sampling signal to obtain 2N reset voltages; and a second sampling module sampling the imaging signal N times under the control of N third sampling signals and a fourth sampling signal to obtain 2N signal voltages; in each cycle of the imaging signal, when the imaging signal is sampled, the amplification module is controlled by the reset signal to perform a reset operation, and after sampling, the 2N reset voltages and the 2N signal voltages are differentially amplified 2N-1 times in sequence to obtain 2N-1 sampling signals.

Abstract: A differential-follower control circuit has been provided, comprising: a follower; an output-voltage following module, which controls a voltage at a control terminal of the follower to vary with an output voltage; a substrate-voltage following module, which controls a substrate voltage of an output transistor of the follower to vary with an input voltage; an output terminal of the follower is connected to a first terminal of the output-voltage following module; a second terminal of the output-voltage following module is connected to the control terminal of the follower; a first terminal of the substrate-voltage following module is connected to an input terminal of the follower and a second terminal of the substrate-voltage following module is connected to a substrate of the output transistor; the invention effectively improves the overall linearity of the follower.

Abstract: The present disclosure provides a polysilicon resistor, a method for manufacturing the same, and a successive approximation register analog-to-digital converter.

Abstract: An analog-to-digital converter includes an input configuration module, an analog-to-digital conversion module, an adaptive parameter extraction module, and a full-period data restoration module. In a parameter extraction working mode, correction parameters are extracted through cooperation of the input configuration module, the analog-to-digital conversion module, the adaptive parameter extraction module, and the full-period data restoration module. In a normal working mode, digital calibration and correction of digital signals are implemented by using the analog-to-digital conversion module and the correction parameters. The correction parameters include a dither correction parameter, a gain correction parameter, and a mismatch error correction parameter.

Abstract: A low-jitter random clock generation circuit includes: a clock division and pulse generation module connected to an input clock, performing frequency division processing to obtain frequency division clocks, and then detecting some frequency division clocks one by one to obtain frequency division pulses in a one-to-one correspondence; a pseudorandom number generation module connected to one frequency division clock, and generating a pseudorandom number; a status control module connected to all the frequency division clocks and the pseudorandom number to generate status control signals; and a random clock output module connected to the input clock, all the frequency division clocks, all the frequency division pulses, and all the status control signals, randomly sampling the frequency division clocks by using the frequency division pulses under control of the status control signals, and synchronously outputting the randomly sampled frequency division clocks by using the input clock, to obtain random clocks.

Abstract: In a pipelined analog-to-digital converter, at least one pipeline stage includes an N-bit sub-analog-to-digital conversion module, a first sub-digital-to-analog conversion module, a second sub-digital-to-analog conversion module, and a switched capacitor amplification module. The first sub-digital-to-analog conversion module and the second sub-digital-to-analog conversion module respectively receive and process 2N?1 digital signals, which correspondingly require 2*2N?1 switched capacitors. In a pipeline stage based on a structure of “N-bit sub-analog-to-digital conversion module+sub-digital-to-analog conversion module+subtractor+multiplier”, the non-inverting input and the inverting input of the differential input comparison are completely symmetrical, which correspondingly requires 2*2N switched capacitors.

Abstract: The comparator includes an input unit, a load unit, a control switch, and an adjustment unit. The input ends of the input unit are connected to a first input signal and a second input signal. The load unit is connected to the input unit, and the gain of the comparator is adjusted by changing the gate voltages of the pair of gain adjustment transistors of the load unit. The adjustment unit is connected to the input unit, and the gate voltages of the pair of gain adjustment transistors are adjusted according to the enable state of the control switch. The present disclosure also provides an analog-to-digital converter.

Abstract: A comparison method includes: providing a successive approximation register analog-to-digital converter, where the successive approximation register analog-to-digital converter includes n?1 weighted capacitors, a charge transfer capacitor, and a comparator; sampling an differential input signal by using the first weighted capacitor and the charge transfer capacitor; importing the differential input signal stored on the charge transfer capacitor, where the differential input signal is transferred and redistributed on the charge transfer capacitor and n?2 other weighted capacitors than the first weighted capacitor, and completing the first time of comparison; and importing the differential input signal stored on the first weighted capacitor and the differential input signal stored on the charge transfer capacitor, importing a reference voltage by using the second to jth weighted capacitors, where the differential input signal and the reference voltage are transferred and redistributed on a capacitor array, and

Abstract: A method for correcting an analog-to-digital converter includes the following steps: extracting gain errors and weight errors of all conversion stages of an analog-to-digital converter; performing first correction on the analog-to-digital converter based on the gain errors and the weight errors; extracting jitter errors of all conversion stages of the analog-to-digital converter after the first correction; and performing a second correction on the analog-to-digital converter based on the jitter errors. According to the disclosure, the gain errors, the weight errors, and the jitter errors of all conversion stages are successively extracted, and then the analog-to-digital converter is corrected. Precision after the corrections is higher.

Abstract: An adaptive current generation circuit includes an inverter drive chain, a frequency divider, a frequency detector, a low-pass filter, a static comparator group, and a controllable current mirror. An input analog signal of the input buffer is converted into a frequency discrimination voltage in a direct current form sequentially through conversion of the inverter drive chain, frequency division of the frequency divider, frequency detection of the frequency detector, and conversion of the low-pass filter. Then the static comparator group performs a plurality of times of comparison to obtain N bits of digital codes. Finally, the controllable current mirror is controlled by using the N bits of digital codes. The controllable current mirror provides a magnitude-adjustable input current for the input buffer under control of the N bits of digital codes. A magnitude of the input current is positively correlated with a frequency of the input analog signal.

Abstract: A comparator based on a pre-amplifier stage structure and an analog-to-digital converter are provided. The comparator includes: a first pre-amplifier stage, where an input terminal of the first pre-amplifier stage is connected to a differential input signal, to amplify and output the differential input signal so as to output a first differential output signal; a second pre-amplifier stage, where an input terminal of the second pre-amplifier stage is connected to the first differential output signal, to amplify and output the first differential output signal so as to output a second differential output signal, and a positive feedback unit is disposed between an output terminal of the second pre-amplifier stage and the input terminal of the second pre-amplifier stage, to increase a voltage gain of the second pre-amplifier stage by using the positive feedback unit; and a latch, an input terminal thereof connected to the second differential output signal.