Patents by Inventor GuangSu SHAO

GuangSu SHAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230171951
    Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor structure includes a plurality of active pillars, a dielectric layer that is disposed around a circumference of the active pillar and that covers a part of a sidewall of the active pillar, and a word line. Any two adjacent ones of the plurality of active pillars are separated by using a first trench or a second trench. The first trench and the second trench are staggered. The second trench is wider than the first trench. The dielectric layer is disposed around the circumference of the active pillars. The word line partially covers the dielectric layer, and fills a part of the first trench located between adjacent active pillars.
    Type: Application
    Filed: June 29, 2022
    Publication date: June 1, 2023
    Inventors: Guangsu SHAO, Deyuan XIAO, Yunsong QIU, Mengkang YU
  • Publication number: 20230171938
    Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of active pillars arranged in an array on the substrate, where the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially, and along a second direction, a cross-sectional area of the second segment is smaller than those of the first segment and the third segment; forming a gate oxide layer on a sidewall of the second segment, a top surface of the first segment, and a bottom surface of the third segment; and forming a gate dielectric layer on the gate oxide layer, where the gate dielectric layer is shorter than the gate oxide layer, and is close to the third segment.
    Type: Application
    Filed: August 4, 2022
    Publication date: June 1, 2023
    Inventors: Deyuan XIAO, Yong Yu, Guangsu Shao
  • Publication number: 20230171941
    Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a substrate; forming active pillars arranged at intervals on the substrate, the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially along a first direction; forming a gate oxide layer on sidewalls of each of the second segment and the third segment; and forming a word line structure on a sidewall of the gate oxide layer, the word line structure includes a first word line structure and a second word line structure that are made of different materials, and the first word line structure is connected to the sidewall of the gate oxide layer, and partially covers the second word line structure.
    Type: Application
    Filed: August 5, 2022
    Publication date: June 1, 2023
    Inventors: Deyuan XIAO, Yong Yu, Guangsu Shao
  • Publication number: 20230171939
    Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of silicon pillars on the substrate, where the silicon pillars are arranged as an array; preprocessing the silicon pillar to form an active pillar, where the active pillar includes a first segment, a second segment, and a third segment; forming a first gate oxide layer on sidewalls of the second segment and the third segment; and forming a second gate oxide layer on the first gate oxide layer, where a length of the second gate oxide layer is less than that of the first gate oxide layer, and a thickness of the second gate oxide layer is greater than that of the first gate oxide layer.
    Type: Application
    Filed: August 9, 2022
    Publication date: June 1, 2023
    Inventors: Deyuan XIAO, Yong YU, Guangsu SHAO
  • Publication number: 20230171952
    Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: an array region, where the array region is provided with a plurality of active pillars; a plurality of bit lines extending along a first direction, where the bit line is located at a bottom of the active pillar; and a plurality of word lines extending along a second direction, where any one of the word lines covers sidewalls of a column of the active pillars arranged along the second direction; and the first direction and the second direction form a predetermined angle, and the predetermined angle is an acute angle or an obtuse angle.
    Type: Application
    Filed: July 22, 2022
    Publication date: June 1, 2023
    Inventors: Deyuan XIAO, Guangsu SHAO
  • Publication number: 20230171940
    Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of silicon pillars arranged in an array on the substrate; pre-processing the silicon pillar, to form an active pillar, where along a first direction, the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially; forming a gate oxide layer on sidewalls of each of the second segment and the third segment; and forming a gate dielectric layer on the gate oxide layer, where along the first direction, the gate dielectric layer is shorter than the gate oxide layer, and a top surface of the gate dielectric layer is flush with that of the third segment.
    Type: Application
    Filed: August 5, 2022
    Publication date: June 1, 2023
    Inventors: Deyuan XIAO, Yong Yu, Guangsu Shao
  • Publication number: 20230140073
    Abstract: The present application relates to a buried gate and a manufacturing method thereof. The method for manufacturing a buried gate includes: providing a substrate; forming a word line trench in the substrate; treating a surface of the word line trench to form concave structures on the surface of the word line trench; and, forming a conductive layer in the word line trench, convex structures matched with the concave structures being provided on a surface of the conductive layer.
    Type: Application
    Filed: May 25, 2021
    Publication date: May 4, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: CHEONG SOO KIM, YONG GUN KIM, Xianrui HU, GuangSu SHAO
  • Patent number: 11637189
    Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a forming method thereof. The forming method includes: providing a base and a plurality of stack structures that are located on the base, arranged at intervals, and extend along a first direction, wherein the stack structures each include a plurality of semiconductor layers arranged at intervals in a direction perpendicular to a surface of the base, and a top surface and a bottom surface opposite to each other of each of the semiconductor layers are each provided with a first sacrificial layer, a surface of the first sacrificial layer that is away from the semiconductor layer is provided with a second sacrificial layer, a same etching process has different etching rates for the first sacrificial layer and the second sacrificial layer, an isolation layer is provided between adjacent ones of the stack structures.
    Type: Grant
    Filed: September 15, 2022
    Date of Patent: April 25, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Guangsu Shao, Deyuan Xiao
  • Publication number: 20230120017
    Abstract: Embodiments provide a semiconductor structure and a method for fabricating the same, and relate to the field of semiconductor technology. The method includes: providing a substrate provided with word line trenches and bit line trenches, where the word line trenches and the bit line trenches separate the substrate into active pillars arranged at intervals, and along a first direction, a dielectric layer is provided between adjacent active pillars; forming initial protective layers on side walls of the word line trenches; forming word line isolation structures in the region surrounded by the initial protective layers, the word line isolation structures having gaps therein; forming sealing members configured to seal up at least tops of the gaps; forming first filling regions; and forming word lines extending along the first direction in the first filling regions. Parasitic capacitance is prevented in the semiconductor structure, and performance of the semiconductor structure is improved.
    Type: Application
    Filed: September 25, 2022
    Publication date: April 20, 2023
    Inventors: Guangsu SHAO, Deyuan XIAO, Yunsong QIU
  • Publication number: 20230066811
    Abstract: The present application provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method includes: providing a substrate, the substrate including a first semiconductor material layer, a silicon-germanium compound layer and a second semiconductor material layer that are stacked sequentially; forming, in the substrate, first trenches extending along a first direction and second trenches extending along a second direction, and the first trenches and the second trenches separating the substrate into a plurality of spaced pillar structures; doping the pillar structures, such that the silicon-germanium compound layer forms a channel region; and forming a dielectric layer on an outer peripheral surface of each of the pillar structures, and a gate on an outer peripheral surface of the dielectric layer, the gate being opposite to at least a part of the channel region.
    Type: Application
    Filed: May 20, 2022
    Publication date: March 2, 2023
    Inventors: Guangsu SHAO, Pan Yuan, Minmin Wu
  • Publication number: 20230061921
    Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method of the semiconductor structure includes: providing a substrate, a plurality of spaced first trenches being formed in the substrate; forming a sacrificial layer in the first trenches and a first protective layer on the sacrificial layer, the sacrificial layer and the first protective layer filling up the first trenches, and the first protective layer in the first trenches being provided with etching holes penetrating through the first protective layer; removing the sacrificial layer with the etching holes to form air gaps; and carrying out a silicification reaction on the substrate between adjacent ones of the first trenches and close to bottoms of the first trenches to form bit lines (BLs) in the substrate, parts of side surfaces of the BLs being exposed in the air gaps.
    Type: Application
    Filed: May 20, 2022
    Publication date: March 2, 2023
    Inventors: Guangsu Shao, Weiping Bai, Deyuan Xiao, Yunsong Qiu
  • Publication number: 20230063571
    Abstract: A method for forming a capacitor, the capacitor and a semiconductor device are provided. The method includes: providing a semiconductor structure including a substrate, a stacked-layer structure, a protective layer, a first mask layer, and a photolithography layer which is provided with a plurality of cross-shaped patterns arranged in a square close-packed manner; patterning the first mask layer based on the photolithography layer; forming a plurality of through holes penetrating through the protective layer and the stacked-layer structure based on the patterned first mask layer by etching, in which in a direction perpendicular to a surface of the substrate, a projection of each through hole is cross-shaped, and the plurality of through holes are arranged in the square close-packed manner; and forming a first electrode layer, a dielectric layer and a second electrode layer covering an inner wall of each through hole to form the capacitor.
    Type: Application
    Filed: June 24, 2022
    Publication date: March 2, 2023
    Inventors: Guangsu SHAO, Mengkang Yu, Xingsong Su
  • Publication number: 20230064521
    Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The method for forming the semiconductor structure includes the following operations. A base is provided, in which the base includes a substrate, a first semiconductor layer and a second semiconductor layer sequentially formed on one another. A plurality of first isolation structures spaced apart from each other and a plurality of second isolation structures spaced apart from each other are formed in the base. A channel layer is formed in the first semiconductor layer, in which a through hole is provided between the channel layer and each of two first isolation structures adjacent to the channel layer. A gate structure is formed in the through hole.
    Type: Application
    Filed: May 31, 2022
    Publication date: March 2, 2023
    Inventors: Guangsu Shao, Deyuan Xiao, Qinghua Han, Yunsong Qiu, Weiping Bai
  • Publication number: 20230063473
    Abstract: Provided is a method for manufacturing a semiconductor structure. It includes: forming first grooves filled with a first dielectric layer and extending in a first direction in a substrate; forming second grooves extending in a second direction in the substrate and the first dielectric layer, the second grooves and the first grooves being intersected and defining discrete active columns in the substrate; depositing second dielectric layers on sidewalls of the second grooves; depositing sacrificial layers in the second grooves, the sacrificial layers being sandwiched between the second dielectric layers; removing part of the first dielectric layer and part of the second dielectric layer, and forming hole structures extending in the second direction, the hole structures surrounding the active columns, and adjacent hole structures being separated by the sacrificial layers; forming word lines in the hole structures; and removing the sacrificial layers to form air gaps between adjacent word lines.
    Type: Application
    Filed: May 23, 2022
    Publication date: March 2, 2023
    Inventors: Guangsu SHAO, Deyuan XIAO, Yunsong QIU
  • Publication number: 20230059600
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The method includes: forming a plurality of first trenches extending in a first direction on the substrate; forming a plurality of second trenches extending in a second direction on the substrate on which the first trenches are formed; forming a first isolation layer in at least one of the first trenches and at least one of the second trenches, in which o first gaps are respectively provided between the first isolation layer and sidewalls on both sides of the first trench; forming two bit lines which are parallel to each other and extend in the first direction by depositing conductive layers of a first conductive material at bottoms of the first gaps on both sides of the first trench; and forming word lines extending in the second direction above the conductive layers in the first trench and the second trench.
    Type: Application
    Filed: June 9, 2022
    Publication date: February 23, 2023
    Inventors: Guangsu Shao, Deyuan Xiao, Yunsong Qiu
  • Publication number: 20230057480
    Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate including a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals in a first direction; in which the bit line isolation trenches extend in a second direction, the first direction being perpendicular to the second direction; forming a bit line isolation layer in a bit line isolation trench; in which a gap is provided between the bit line isolation layer and the bit line isolation trench, in which the gap is located at a bottom corner of the bit line isolation trench and extends in the second direction, and exposes part of the bottom of the bit line isolation trench; etching a first semiconductor pillar in the first direction through the gap to form a bit line trench; forming a bit line in the bit line trench.
    Type: Application
    Filed: July 4, 2022
    Publication date: February 23, 2023
    Applicants: CHANGXIN MEMORY TECHNOLOGIES, INC., BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY
    Inventors: Guangsu SHAO, Deyuan XIAO, Yunsong QIU, Minmin WU
  • Publication number: 20230049171
    Abstract: Embodiments provide a semiconductor structure and a fabrication method thereof. The fabrication method includes: providing a substrate including a plurality of semiconductor layers arranged at intervals and an isolation layer positioned between adjacent two of the plurality of semiconductor layers, a given one of the plurality of semiconductor layers and the isolation layer being internally provided with trenches, and each of the trenches including a first region, a second region and a third region sequentially distributed; forming a sacrificial layer on an inner wall of the trench in the first region and the second region; forming an insulating layer filling up the trench on a surface of the sacrificial layer; removing the sacrificial layer in the second region, and removing the isolation layer of a first thickness to form voids surrounding the given semiconductor layer.
    Type: Application
    Filed: August 1, 2022
    Publication date: February 16, 2023
    Inventors: Guangsu SHAO, Deyuan XIAO, Weiping BAI, Yunsong QIU
  • Publication number: 20230029936
    Abstract: Embodiments relate to a semiconductor structure and a method for fabricating the same. The method includes: providing a substrate; forming a first isolation trench in the substrate; filling a first isolation dielectric layer in the first isolation trench; forming a second isolation trench; forming a second isolation dielectric layer in the second isolation trench; forming word line structures arranged at intervals, where the word line structures extend along the second direction to wrap the channel regions of the active pillars in a same row; etching back the second isolation dielectric layer and the first isolation dielectric layer to expose second connection terminals of the active pillars; and forming a protective layer configured to define positions of the word line structures and wrap the second connection terminals of the active pillars.
    Type: Application
    Filed: September 25, 2022
    Publication date: February 2, 2023
    Inventor: Guangsu SHAO
  • Publication number: 20230025471
    Abstract: Embodiments relate to a semiconductor structure and a method for fabricating. The semiconductor structure includes: a substrate, word lines, bit lines, and word line isolation structures. Active pillars arranged in an array are provided on a surface of the substrate, and the active pillars include channel regions, and a top doped region positioned on an upper side of the channel region and a bottom doped region positioned on a lower side of the channel region. The word lines extend along a first direction and surround the channel regions of a row of the active pillars arranged along the first direction. The bit lines extend along a second direction and are electrically connected to the bottom doped regions of a column of the active pillars arranged along the second direction, and in a direction facing away from the surface of the substrate.
    Type: Application
    Filed: September 27, 2022
    Publication date: January 26, 2023
    Inventors: Guangsu SHAO, Deyuan XIAO
  • Publication number: 20230013070
    Abstract: A semiconductor device and a formation method thereof are provided. The semiconductor device includes: a semiconductor substrate, where a plurality of columnar active areas are formed on the semiconductor substrate, the plurality of columnar active areas are spaced apart by a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction; a plurality of third trenches positioned in the semiconductor substrate at bottoms of the second trenches, where the third trenches are recessed to bottoms of the columnar active areas, and a bottom surface of a given one of the third trenches is higher than a bottom surface of the given first trench; and a plurality of metal silicide bit lines extending along the first direction in the semiconductor substrate positioned at the bottoms of the plurality of third trenches and the bottoms of the plurality of columnar active areas.
    Type: Application
    Filed: September 22, 2022
    Publication date: January 19, 2023
    Inventors: Guangsu SHAO, Deyuan XIAO, Yunsong QIU, Yuhan ZHU