Patents by Inventor Gun Heo
Gun Heo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240122053Abstract: Provided are display panel manufacturing method and apparatus. The display panel manufacturing method includes detecting a machining target area of a bottom layer, removing an area, overlapping the machining target area, of a top layer, emitting a laser beam to the machining target area of the bottom layer to provide a bottom pattern from the machining target area, and providing a compensation pattern in the removed area of the top layer.Type: ApplicationFiled: October 10, 2023Publication date: April 11, 2024Inventors: SUNGJUN KIM, WOO HYUK KWON, JAE MYOUN DO, BONG HO SUL, SEUNG NOH LEE, GYEOM UK KIM, YOUNG-BAE KIM, YOUNG-JUN YUN, KYUNGCHEOL LEE, KYUNGSEOK HEO, GUN-A HWANG, MINHO HWANG
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Publication number: 20240080994Abstract: In fabricating a wiring structure, a first wiring is formed on a substrate. First and second light sensitive insulation layers that are reactive to light of first and second wavelength ranges, respectively, are sequentially formed on the first wiring. First and second exposing processes are performed using the light of the first and second wavelength ranges, respectively, to form first and second exposed portions in the first and second light sensitive insulation layers, respectively. The first and second exposed portions are removed by a developing process to form a hole and an opening, respectively. The hole and the opening extend through the first and second light sensitive insulation layers, respectively, to be connected to one another. A conductive layer is formed in the hole and in the opening, and is planarized to form a first via and a second wiring in the hole and in the opening, respectively.Type: ApplicationFiled: August 9, 2023Publication date: March 7, 2024Inventors: Gun Lee, Junwoo Myung, Yuseon Heo
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Publication number: 20240071262Abstract: An electronic price indicator according to an embodiment includes a display displaying product information, an NFC module configured to communicate with a user terminal, a Bluetooth module configured to communicate with the user terminal, and a processor configured to control the display to display the product information received from the user terminal through the Bluetooth module. The processor is further configured to release a sleep mode when receiving an interrupt from the user terminal through the NFC module, and perform Bluetooth communication with the user terminal by initiating a scan for a predetermined period of time to receive an advertising signal from the user terminal.Type: ApplicationFiled: January 20, 2023Publication date: February 29, 2024Inventors: Jae Gun HEO, Chung Hee LEE, Do Sang KWON, Woo Seok HAN, Chan LEE, Ji Hoon KIM, Bo II SEO
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Publication number: 20230418179Abstract: An example image forming apparatus includes a main body having a guide frame to guide a toner cartridge on a path for detachment and attachment, a sensor to sense a remaining toner level of the toner cartridge, and a shutter member disposed to move along the guide frame in association with the attachment and detachment of the toner cartridge. In response to separation of the toner cartridge from the guide frame, the shutter member is movable to a first position covering the sensor and, in response to the toner cartridge being mounted on the guide frame, the shutter member is movable to a second position to open the sensor.Type: ApplicationFiled: December 6, 2022Publication date: December 28, 2023Inventors: Gun HEO, Hojin JANG, Jaerae LEE
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Patent number: 11835884Abstract: An example image forming apparatus includes a main body having a guide frame to guide a toner cartridge on a path for detachment and attachment, a sensor to sense a remaining toner level of the toner cartridge, and a shutter member disposed to move along the guide frame in association with the attachment and detachment of the toner cartridge. In response to separation of the toner cartridge from the guide frame, the shutter member is movable to a first position covering the sensor and, in response to the toner cartridge being mounted on the guide frame, the shutter member is movable to a second position to open the sensor.Type: GrantFiled: December 6, 2022Date of Patent: December 5, 2023Assignee: Hewlett-Packard Development Company, L.P.Inventors: Gun Heo, Hojin Jang, Jaerae Lee
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Publication number: 20230273566Abstract: A toner cartridge includes: a housing to accommodate toner and including a fastening boss at a front end; a front cover including a fastening hole aligned with the fastening boss; a fastening member including a fastening portion and a head portion, the fastening portion configured to pass through the fastening hole and be fastened to the fastening boss to couple the front cover to the housing; and a separating portion to allow the fastening hole to be separated from the head portion of the fastening member by an external force acting on the front cover.Type: ApplicationFiled: November 17, 2020Publication date: August 31, 2023Applicant: Hewlett-Packard Development Company, L.P.Inventors: Jinsam PARK, Jinhong KIM, Gun HEO, Seongwoong YANG
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Patent number: 11460952Abstract: Disclosed herein are an apparatus and method for automatically calibrating capacitance per channel, for measuring parasitic capacitance values of respective channels due to a difference in a length of a wiring of each capacitance sensing channel when a circuit is designed and adding a unique calibration capacitance value of each channel such that all channels have the same reference capacitance value that is preset, and in detail, the apparatus for automatically calibrating a capacitance per channel includes a touch sensing device including a plurality of touch sensing regions, and a capacitance measurement and calibration device configured to measure parasitic capacitances of channels connected to the plurality of touch sensing regions, respectively, and to add a unique calibration capacitance of each channel to a corresponding channel to acquire a preset reference capacitance when each channel is connected to the parasitic capacitance.Type: GrantFiled: April 6, 2020Date of Patent: October 4, 2022Assignee: ABOV SEMICONDUCTOR CO., LTD.Inventors: Young Jin Seo, Young Gun Heo
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Publication number: 20200371144Abstract: Disclosed herein are an apparatus and method for automatically calibrating capacitance per channel, for measuring parasite capacitance values of respective channels due to a difference in a length of a wiring of each capacitance sensing channel when a circuit is designed and adding a unique calibration capacitance value of each channel such that all channels have the same reference capacitance value that is preset, and in detail, the apparatus for automatically calibrating a capacitance per channel includes a touch sensing device including a plurality of touch sensing regions, and a capacitance measurement and calibration device configured to measure parasite capacitances of channels connected to the plurality of touch sensing regions, respectively, and to add a unique calibration capacitance of each channel to a corresponding channel to acquire a preset reference capacitance when each channel is connected to the parasite capacitance.Type: ApplicationFiled: April 6, 2020Publication date: November 26, 2020Inventors: Young Jin SEO, Young Gun Heo
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Patent number: 10504726Abstract: A nanoscale structure includes an array of pillars over an underlying layer, a separation wall layer including first separation walls formed over sidewalls of the pillars, and a block co-polymer (BCP) layer formed over the separation wall layer and filling gaps between the pillars. The BCP layer is phase-separated to include first domains that provide second separation walls formed over the first separation walls and second domains that are separated from each other by the first domains.Type: GrantFiled: June 16, 2017Date of Patent: December 10, 2019Assignee: SK HYNIX INC.Inventors: Keun Do Ban, Jung Gun Heo, Cheol Kyu Bok, Myoung Soo Kim
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Patent number: 9911605Abstract: A method of forming fine patterns includes forming pillars arrayed in rows and columns on an underlying layer and forming a spacer layer on the underlying layer to cover the pillars. Portions of the spacer layer respectively covering the pillars arrayed in each row or in each column are in contact with each other to provide first interstitial spaces disposed between the pillars arrayed in a diagonal direction between a row direction and a column direction as well as to provide cleavages at corners of each of the first interstitial spaces in a plan view. A healing layer is formed on the spacer layer to fill the cleavages of the first interstitial spaces. The healing layer is formed to provide second interstitial spaces respectively located in the first interstitial spaces as well as to include a polymer material.Type: GrantFiled: August 15, 2016Date of Patent: March 6, 2018Assignee: SK Hynix Inc.Inventors: Jung Gun Heo, Hong Ik Kim, Keun Do Ban, Cheol Kyu Bok, Young Sik Kim
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Publication number: 20170287702Abstract: A nanoscale structure includes an array of pillars over an underlying layer, a separation wall layer including first separation walls formed over sidewalls of the pillars, and a block co-polymer (BCP) layer formed over the separation wall layer and filling gaps between the pillars. The BCP layer is phase-separated to include first domains that provide second separation walls formed over the first separation walls and second domains that are separated from each other by the first domains.Type: ApplicationFiled: June 16, 2017Publication date: October 5, 2017Inventors: Keun Do BAN, Jung Gun HEO, Cheol Kyu BOK, Myoung Soo KIM
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Publication number: 20170271149Abstract: A method of forming fine patterns includes forming pillars arrayed in rows and columns on an underlying layer and forming a spacer layer on the underlying layer to cover the pillars. Portions of the spacer layer respectively covering the pillars arrayed in each row or in each column are in contact with each other to provide first interstitial s paces disposed between the pillars arrayed in a diagonal direction between a row direction and a column direction as well as to provide cleavages at corners of each of the first interstitial spaces in a plan view. A healing layer is formed on the spacer layer to fill the cleavages of the first interstitial spaces. The healing layer is formed to provide second interstitial spaces respectively located in the first interstitial spaces as well as to include a polymer material.Type: ApplicationFiled: August 15, 2016Publication date: September 21, 2017Inventors: Jung Gun HEO, Hong Ik KIM, Keun Do BAN, Cheol Kyu BOK, Young Sik KIM
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Patent number: 9691614Abstract: A method includes forming a template portion to provide a first opening trench portion surrounding a first isolated pattern, and forming an array of pillars on an underlying layer; forming a separation wall layer including first separation wall portions surrounding sidewalls of the pillars, and forming second separation wall portions covering sidewalls of the first opening trench portion; forming a block copolymer layer on the separation wall layer; forming first domains in gaps between the pillars, and forming second domains surrounding and separating the first domains by annealing the block copolymer layer; forming second openings by selectively removing the first domains; forming third openings between the second openings, and forming a fourth opening adjacent to the first isolated pattern by selectively removing the pillars and the template portion; and forming fifth openings, which extend from the second and third openings and penetrate the underlying layer, and forming a sixth opening, which extends froType: GrantFiled: August 22, 2016Date of Patent: June 27, 2017Assignee: SK Hynix Inc.Inventors: Keun Do Ban, Jong Cheon Park, Jung Gun Heo, Hong Ik Kim, Cheol Kyu Bok
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Patent number: 9684265Abstract: Provided is a developing device configured to develop an electrostatic latent image formed on an image bearing member by feeding a toner to the electrostatic latent image. The developing device includes a developing frame configured to form an inner space in which the toner and a carrier are to be mixed, a developing roller including an outer periphery to which the developer attaches where the developing roller feeds the toner included in the developer to the image bearing member. The developing device includes an agitator installed in the inner space and configured to mix and deliver the toner and the carrier in a direction parallel to an axial direction of the developing roller, and a plurality of concave portions arranged on a bottom surface of the developing frame.Type: GrantFiled: March 9, 2016Date of Patent: June 20, 2017Assignee: S-PRINTING SOLUTION CO., LTD.Inventors: Jong-hyun Park, Gun Heo
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Patent number: 9666448Abstract: A method of forming patterns includes forming an array of pillars on an underlying layer stacked on an etch target layer, forming a separation wall layer on the pillars to provide separation walls covering sidewalls of the pillars, forming a block copolymer layer on the separation wall layer, annealing the block copolymer layer to form first domains located between the pillars, and a second domain surrounding and isolating the first domains, selectively removing the first domains to form second openings, selectively removing the pillars to form fourth openings, forming fifth openings that extend from the second and fourth openings to penetrate the underlying layer, forming a sealing pattern that covers and seals dummy openings among the fifth openings, and forming seventh openings that extend from the fifth openings exposed by the sealing pattern to penetrate the etch target layer.Type: GrantFiled: August 27, 2015Date of Patent: May 30, 2017Assignee: SK Hynix Inc.Inventors: Keun Do Ban, Hong Ik Kim, Jung Gun Heo, Cheol Kyu Bok
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Patent number: 9640399Abstract: A method of forming patterns includes forming a guide pattern and first peripheral patterns on an underlying layer. The guide pattern provides first openings and the first peripheral patterns provide a fifth opening used in alignment of the guide pattern. An alignment status of the guide pattern is verified using the fifth opening. A block copolymer layer is formed to fill the first and fifth openings. The block copolymer layer is annealed to provide a blocking portion sealing the fifth opening and to form first domains in each first opening and a second domain surrounding the first domains formed in each first opening. The first domains are removed to form third openings. The underlying layer is etched using the blocking portion and sidewalls of the second domains as etch barriers to form fourth openings that extend from the third openings to penetrate the underlying layer.Type: GrantFiled: August 11, 2015Date of Patent: May 2, 2017Assignee: SK Hynix Inc.Inventors: Jung Gun Heo, Hong Ik Kim, Keun Do Ban, Cheol Kyu Bok
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Patent number: 9523917Abstract: Methods of forming patterns includes guide patterns on a neutral layer. A self-assembling block copolymer (BCP) layer on the guide patterns and the neutral layer. By annealing the self-assembling BCP layer, first polymer block domains and second polymer block domains are formed The guide patterns are formed of a developable antireflective material. The neutral layer is formed of a cross-linked polymeric material.Type: GrantFiled: April 25, 2016Date of Patent: December 20, 2016Assignee: SK Hynix Inc.Inventors: Keun Do Ban, Cheol Kyu Bok, Jung Gun Heo, Hong Ik Kim
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Publication number: 20160358771Abstract: A method includes forming a template portion to provide a first opening trench portion surrounding a first isolated pattern, and forming an array of pillars on an underlying layer; forming a separation wall layer including first separation wall portions surrounding sidewalls of the pillars, and forming second separation wall portions covering sidewalls of the first opening trench portion; forming a block copolymer layer on the separation wall layer; forming first domains in gaps between the pillars, and forming second domains surrounding and separating the first domains by annealing the block copolymer layer; forming second openings by selectively removing the first domains; forming third openings between the second openings, and forming a fourth opening adjacent to the first isolated pattern by selectively removing the pillars and the template portion; and forming fifth openings, which extend from the second and third openings and penetrate the underlying layer, and forming a sixth opening, which extends froType: ApplicationFiled: August 22, 2016Publication date: December 8, 2016Inventors: Keun Do BAN, Jong Cheon PARK, Jung Gun HEO, Hong Ik KIM, Cheol Kyu BOK
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Publication number: 20160293443Abstract: A method includes forming a template portion to provide a first opening trench portion surrounding a first isolated pattern, and forming an array of pillars on an underlying layer; forming a separation wall layer including first separation wall portions surrounding sidewalls of the pillars, and forming second separation wall portions covering sidewalls of the first opening trench portion; forming a block copolymer layer on the separation wall layer; forming first domains in gaps between the pillars, and forming second domains surrounding and separating the first domains by annealing the block copolymer layer; forming second openings by selectively removing the first domains; forming third openings between the second openings, and forming a fourth opening adjacent to the first isolated pattern by selectively removing the pillars and the template portion; and forming fifth openings, which extend from the second and third openings and penetrate the underlying layer, and forming a sixth opening, which extends froType: ApplicationFiled: September 10, 2015Publication date: October 6, 2016Inventors: Keun Do BAN, Jong Cheon PARK, Jung Gun HEO, Hong Ik KIM, Cheol Kyu BOK
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Publication number: 20160293442Abstract: A method of forming patterns includes forming an array of pillars on an underlying layer stacked on an etch target layer, forming a separation wall layer on the pillars to provide separation walls covering sidewalls of the pillars, forming a block copolymer layer on the separation wall layer, annealing the block copolymer layer to form first domains located between the pillars, and a second domain surrounding and isolating the first domains, selectively removing the first domains to form second openings, selectively removing the pillars to form fourth openings, forming fifth openings that extend from the second and fourth openings to penetrate the underlying layer, forming a sealing pattern that covers and seals dummy openings among the fifth openings, and forming seventh openings that extend from the fifth openings exposed by the sealing pattern to penetrate the etch target layer.Type: ApplicationFiled: August 27, 2015Publication date: October 6, 2016Inventors: Keun Do BAN, Hong Ik KIM, Jung Gun HEO, Cheol Kyu BOK