Patents by Inventor Guo-cheng Liao

Guo-cheng Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11107777
    Abstract: A substrate structure includes a substrate body, a bottom circuit layer, a first bottom protection structure and a second bottom protection structure. The substrate body has a top surface and a bottom surface opposite to the top surface. The bottom circuit layer is disposed adjacent to the bottom surface of the substrate body, and includes a plurality of pads. The first bottom protection structure is disposed on the bottom surface of the substrate body, and covers a portion of the bottom circuit layer. The second bottom protection structure is disposed on the bottom surface of the substrate body, and covers a portion of the bottom circuit layer. A second thickness of the second bottom protection structure is greater than a first thickness of the first bottom protection structure.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: August 31, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng Liao, Yi Chuan Ding
  • Publication number: 20210226317
    Abstract: A semiconductor device package is provided that includes a substrate, a first support structure disposed on the substrate and a first antenna. The first support structure includes a first surface spaced apart from the substrate by a first distance. The first antenna is disposed above the first surface of the first support structure.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Guo-Cheng LIAO, Yi Chuan DING
  • Publication number: 20210225741
    Abstract: A lead frame includes a die paddle, a first lead, a second lead, an extending portion and at least one supporting portion. The first lead includes a first main portion and a first I/O portion opposite to the first main portion. The second lead includes a second main portion and a second I/O portion opposite to the second main portion. The first lead and the second lead surround the die paddle. The extending portion extends from the first main portion of the first lead. The supporting portion is connected to the extending portion.
    Type: Application
    Filed: January 22, 2020
    Publication date: July 22, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: I-Jen CHEN, Guo-Cheng LIAO, Jyun-Chi JHAN, Hui-Chen HSU
  • Publication number: 20210225742
    Abstract: Present disclosure provides a lead frame, including a die paddle and a plurality of leads surrounding the die paddle. Each of the leads including a finger portion proximal to the die paddle and a lead portion distal from the die paddle. The finger portion includes a main body and at least one support structure. The respective support structures on adjacent leads are mutually isolated, and a distance between the support structure and the die paddle is smaller than a distance between the lead portion and the die paddle. A semiconductor package structure including the lead frame described herein and a semiconductor package assembly including the semiconductor package structure described herein are also provided.
    Type: Application
    Filed: January 22, 2020
    Publication date: July 22, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Jyun-Chi JHAN, Guo-Cheng LIAO
  • Publication number: 20210202410
    Abstract: A semiconductor device package includes a first surface and a second surface opposite to the first surface. The semiconductor device package further includes a first supporting structure disposed on the first surface of the substrate and a second supporting structure disposed on the first surface of the substrate. The first supporting structure has a first surface spaced apart from the first surface of the substrate by a first distance. The second supporting structure has a first surface spaced apart from the first surface of the substrate by a second distance. The second distance is different from the first distance. The semiconductor device package further includes a first antenna disposed above the first surface of the substrate. The first antenna is supported by the first surface of the first supporting structure and the first surface of the second supporting structure.
    Type: Application
    Filed: December 31, 2019
    Publication date: July 1, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Guo-Cheng LIAO, Yi Chuan DING
  • Publication number: 20210125945
    Abstract: A semiconductor device package includes a substrate, a support structure and a first antenna. The substrate has a first surface and a second surface opposite to the first surface. The support structure is disposed on the first surface of the substrate. The first antenna is disposed on the support structure. The first antenna has a first surface facing the substrate, a second surface opposite to the first surface and a lateral surface extending between the first surface and a second surface of the first antenna. The lateral surface of the first antenna is exposed to the external of the semiconductor device package. The first antenna includes a dielectric layer and an antenna pattern disposed within the dielectric layer and penetrating the dielectric layer.
    Type: Application
    Filed: October 24, 2019
    Publication date: April 29, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ting Ruei CHEN, Guo-Cheng LIAO
  • Patent number: 10971798
    Abstract: A semiconductor device package is provided that includes a substrate, a first support structure disposed on the substrate and a first antenna. The first support structure includes a first surface spaced apart from the substrate by a first distance. The first antenna is disposed above the first surface of the first support structure. The first antenna has a first surface, a second surface opposite the first surface and a third surface extending from the first surface to the second surface, wherein the first surface and the second surface of the first antenna are exposed.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: April 6, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng Liao, Yi Chuan Ding
  • Patent number: 10847470
    Abstract: A semiconductor package structure includes a first conductive structure, a second conductive structure, a first semiconductor component, a second semiconductor component and a first encapsulant. The first semiconductor component is disposed on the first conductive structure. The first conductive structure includes a first redistribution layer. The second semiconductor component is disposed on the second conductive structure. The second conductive structure includes a second redistribution layer, and the first conductive structure is electrically connected to the second conductive structure. The first encapsulant covers the first semiconductor component and the first conductive structure. A lateral surface of the first conductive structure and a lateral surface of the first encapsulant are non-coplanar.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: November 24, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng Liao, Chia Ching Chen, Yi Chuan Ding
  • Publication number: 20200127366
    Abstract: A semiconductor device package is provided that includes a substrate, a first support structure disposed on the substrate and a first antenna. The first support structure includes a first surface spaced apart from the substrate by a first distance. The first antenna is disposed above the first surface of the first support structure.
    Type: Application
    Filed: April 4, 2019
    Publication date: April 23, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Guo-Cheng LIAO, Yi Chuan DING
  • Publication number: 20200126881
    Abstract: A package substrate includes a first dielectric layer, a first patterned conductive layer and a first set of alignment marks. The first patterned conductive layer is disposed on the first dielectric layer. The first set of alignment marks is disposed on the first dielectric layer and adjacent to a first edge of the first dielectric layer. The first set of alignment marks includes a plurality of alignment marks. Distances between the alignment marks of the first set of alignment marks and the first edge are different from each other.
    Type: Application
    Filed: October 3, 2019
    Publication date: April 23, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Guo-Cheng LIAO, Yi Chuan DING
  • Publication number: 20190363056
    Abstract: A substrate structure includes a substrate body, a bottom circuit layer, a first bottom protection structure and a second bottom protection structure. The substrate body has a top surface and a bottom surface opposite to the top surface. The bottom circuit layer is disposed adjacent to the bottom surface of the substrate body, and includes a plurality of pads. The first bottom protection structure is disposed on the bottom surface of the substrate body, and covers a portion of the bottom circuit layer. The second bottom protection structure is disposed on the bottom surface of the substrate body, and covers a portion of the bottom circuit layer. A second thickness of the second bottom protection structure is greater than a first thickness of the first bottom protection structure.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 28, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Guo-Cheng LIAO, Yi Chuan DING
  • Publication number: 20190244907
    Abstract: A semiconductor package structure includes a first conductive structure, a second conductive structure, a first semiconductor component, a second semiconductor component and a first encapsulant. The first semiconductor component is disposed on the first conductive structure. The first conductive structure includes a first redistribution layer. The second semiconductor component is disposed on the second conductive structure. The second conductive structure includes a second redistribution layer, and the first conductive structure is electrically connected to the second conductive structure. The first encapsulant covers the first semiconductor component and the first conductive structure. A lateral surface of the first conductive structure and a lateral surface of the first encapsulant are non-coplanar.
    Type: Application
    Filed: February 5, 2018
    Publication date: August 8, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Guo-Cheng LIAO, Chia Ching CHEN, Yi Chuan DING
  • Patent number: 9978705
    Abstract: A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: May 22, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng Liao, Chia-Ching Chen, Yi-Chuan Ding
  • Publication number: 20160336287
    Abstract: A semiconductor package structure includes a substrate, a semiconductor chip, and a solder material. The substrate includes an insulating layer, a conductive circuit layer, and a conductive bump. The conductive circuit layer is recessed from a top surface of the insulating layer. The conductive circuit layer includes a pad, and a side surface of the pad extends along a side surface of the insulating layer. The conductive bump is disposed on the pad. A side surface of the conductive bump, a top surface of the pad and the side surface of the insulating layer together define an accommodating space. A solder material electrically connects the conductive bump and the semiconductor chip. A portion of the solder material is disposed in the accommodating space.
    Type: Application
    Filed: July 28, 2016
    Publication date: November 17, 2016
    Inventors: Guo-Cheng LIAO, Chia-Ching CHEN, Yi-Chuan DING
  • Patent number: 9437565
    Abstract: The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 6, 2016
    Assignee: ADVANCED SEMINCONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng Liao, Chia-Ching Chen, Yi-Chuan Ding
  • Publication number: 20160190079
    Abstract: The present disclosure relates to a semiconductor package structure including a semiconductor substrate, a semiconductor chip and a conductive material. The semiconductor substrate includes an insulating layer, a conductive circuit layer and a conductive bump. The conductive circuit layer is recessed from the top surface of the insulating layer, and includes at least one pad. The conductive bump is disposed on the at least one pad. A side surface of the conductive bump, a top surface of the at least one pad and a side surface of the insulating layer together define an accommodating space. The conductive material is electrically connected the conductive bump and the semiconductor chip, and a portion of the conductive material is disposed in the accommodating space.
    Type: Application
    Filed: December 30, 2014
    Publication date: June 30, 2016
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Guo-Cheng LIAO, Chia-Ching CHEN, Yi-Chuan DING
  • Patent number: 9117697
    Abstract: The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: August 25, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Che Lee, Yuan-Chang Su, Wen-Chi Cheng, Guo-Cheng Liao, Yi-Chuan Ding
  • Publication number: 20140367837
    Abstract: The present disclosure relates to a semiconductor substrate and a method for making the same. The semiconductor substrate includes an insulation layer, a first circuit layer, a second circuit layer, a plurality of conductive vias and a plurality of bumps. The first circuit layer is embedded in a first surface of the insulation layer, and exposed from the first surface of the insulation layer. The second circuit layer is located on a second surface of the insulation layer and electrically connected to the first circuit layer through the conductive vias. The bumps are directly located on part of the first circuit layer, where the lattice of the bumps is the same as that of the first circuit layer.
    Type: Application
    Filed: June 12, 2014
    Publication date: December 18, 2014
    Inventors: Chun-Che LEE, Yuan-Chang SU, Wen-Chi CHENG, Guo-Cheng LIAO, Yi-Chuan DING
  • Publication number: 20140001621
    Abstract: A semiconductor package includes leads around the periphery of a chip and leads under the chip having connecting segments for increasing I/O capability. A filling material may be used under the chip, which may provide a lead locking function. Various methods of forming the semiconductor package are further provided.
    Type: Application
    Filed: August 26, 2013
    Publication date: January 2, 2014
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Guo-Cheng Liao
  • Patent number: 8531017
    Abstract: A semiconductor package includes leads around the periphery of a chip and leads under the chip having connecting segments for increasing I/O capability. A filling material may be used under the chip, which may provide a lead locking function. Various methods of forming the semiconductor package are further provided.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: September 10, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Guo-Cheng Liao