Patents by Inventor Guo-cheng Liao

Guo-cheng Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080157305
    Abstract: A chip package structure including a circuit board, a solder mask, and a chip package is provided. The circuit board has at least one contact on its surface. The solder mask covers the circuit board and has at least one first opening for exposing the contact. The chip package is disposed on the circuit board, and includes a chip and a leadframe, which has at least one lead that is electrically connected to the chip. The lead has an insertion portion that corresponds to the contact and inserts into the first opening. A solder bump is filled into the first opening and fastened to the insertion portion, thereby the connection between the lead and the contact of the chip package structure is secured.
    Type: Application
    Filed: July 23, 2007
    Publication date: July 3, 2008
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Guo-Cheng Liao
  • Publication number: 20080060194
    Abstract: A method for fabricating a passive circuit in a circuit substrate is provided. The circuit substrate comprising a first metallic layer, a second metallic layer, and a dielectric layer is provided firstly, and the dielectric layer is disposed between the first metallic layer and the second metallic layer. Thereafter, a strip shaped through hole through the circuit substrate is formed. Afterward, a third metallic layer is formed on a part of a wall of the strip shaped through hole, and the third metallic layer is electrically connected to the first metallic layer and/or the second metallic layer. The third metallic layer functions as the passive circuit.
    Type: Application
    Filed: July 30, 2007
    Publication date: March 13, 2008
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Guo-Cheng Liao
  • Publication number: 20080053690
    Abstract: A manufacturing method and structure for substrate with vertically embedded capacitors includes the steps of providing a plurality of conductive layers having a first dielectric layer and a leading wire layer formed on the first dielectric layer, providing a plurality of composite layers having a second dielectric layer and a patterned electrode layer formed on the second dielectric layer, laminating the conductive layers and the composite layers to form a block which defines a plurality of substrates with vertically embedded capacitors and a plurality of sawing streets between the substrates, and sawing the block along the sawing streets to singularize the substrates.
    Type: Application
    Filed: May 30, 2007
    Publication date: March 6, 2008
    Inventor: Guo-Cheng Liao
  • Publication number: 20070235870
    Abstract: A common assembly substrate for carrying a die and applying the mechanisms are provided, wherein the common assembly substrate comprises a plurality of bonding fingers formed on one side of the substrate. A bonding wire is used to electrically connect the die with one of the bonding fingers, wherein at least two of the bonding fingers are located in the direction of the bonding wire.
    Type: Application
    Filed: December 6, 2006
    Publication date: October 11, 2007
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING INC.
    Inventor: Guo-Cheng Liao