Abstract: In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.

Abstract: A method, system and program product that implements area minimization of a circuit design while respecting the explicit and implicit design constraints, in the form of ground rules and user intent. A longest path algorithm is used to generate a scaling factor. The scaling factor is used to reduce the size of the circuit design to the minimum legal size. The scaling may be followed by application of minpert analysis to correct any errors introduced by the scaling. The resulting design is shrunk (or expanded) with all elements shrinking (or growing) together by the same factor, and with the relative relationships of elements maintained. In addition, the invention is operational in the presence of a positive cycle, can be run with scaling that freezes the sizes of any structure or ground rule, and can be applied to technology migration.

Abstract: A method and a system for improving manufacturing productivity of an integrated circuit. The method including: (a) generating a set of physical design rules, (b) assigning a rule scoring equation to each physical design rule of the set of physical design rules; (c) checking a physical design of the integrated circuit for deviations from each design rule; (d) computing a score for each physical design rule, using the corresponding rule scoring equation assigned to each physical design rule, for which one or more deviations were found in step (c); and (e) computing a productivity score for the integrated circuit design based on the scores computed in step (d).

Abstract: A method (300) and system (500) for optimizing a circuit layout based on layout constraints (308) and objectives (312). The method includes solving a linear program so as to obtain a rational solution whose variables are either whole or half integer. The tight constraints and objectives involving variables whose solution are a half integer are reduced to a 2-SAT problem, which is analyzed to determine its satisfiability. If the 2-SAT problem is not satisfiable, one or more objectives are removed so as to make the 2-SAT problem satisfiable. Any half-integer results of the linear program are rounded according to the truth assignment that satisfies the 2-SAT problem. The rounded results are used to create the circuit layout.

Abstract: The invention provides a method of modifying a hierarchical integrated circuit layout wherein the locations of hierarchical layout elements are represented with variables and formulae using these variables, which produces a formula-based hierarchical layout. These variables are constrained to be integers. The invention provides for a method for guiding the modification of the layout through an objective function defined on the same variables as the formula-based hierarchical layout. The invention simplifies the formula-based hierarchical layout by substituting constants for some of the variables, such that each of the formulae are reduced to expressions involving no more than two remaining variables. This produces a simplified layout equation and a simplified objective function. This also produces a partial solution to the hierarchical layout modification made up of the values selected for the constants.

Abstract: The invention provides a method and structure for optimizing placement of redundant vias within an integrated circuit design. The invention first locates target vias by determining which vias do not have a redundant via. Then, the invention draws marker shapes on or adjacent to the target vias. The marker shapes are only drawn in a horizontal or vertical direction from each of the target vias. The invention simultaneously expands all of the marker shapes in the first direction to a predetermined length or until the marker shapes reach the limits of a ground rule. During the expanding, different marker shapes will be expanded to different lengths. The invention determines which of the marker shapes were expanded sufficiently to form a valid redundant via to produce a first set of potential redundant vias and the invention eliminates marker shapes that could not be expanded sufficiently to form a valid redundant via.

Abstract: The current invention provides a modification procedure that reduces errors in integrated circuits due to via shorts while at the same time avoiding the unnesting of the layout design and thereby permitting verification of the layout design by LVS testing tools. The current invention identifies if potentially shorting vias have electrically redundant paths and, if so, creates cloned cells of the original cell but void of the potentially shorting vias. The cloned cell is electrically comparable to the original cell. In addition, each instantiation of the original cell in the shapes data base is replaced with the cloned cell when electrical redundancy is present. Also, the number of vias removed can be minimized or maximized while, at the same time, all via electrical shorts are removed, depending on the design requirements.

Abstract: In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.

Abstract: The invention provides a method of modifying a hierarchical integrated circuit layout wherein the locations of hierarchical layout elements are represented with variables and formulae using these variables, which produces a formula-based hierarchical layout. These variables are constrained to be integers. The invention provides for a method for guiding the modification of the layout through an objective function defined on the same variables as the formula-based hierarchical layout. The invention simplifies the formula-based hierarchical layout by substituting constants for some of the variables, such that each of the formulae are reduced to expressions involving no more than two remaining variables. This produces a simplified layout equation and a simplified objective function. This also produces a partial solution to the hierarchical layout modification made up of the values selected for the constants.

Abstract: A method of computing a manufacturing yield of an integrated circuit having device shapes includes sub-dividing the integrated circuit into failure mechanism subdivisions (each of the failure mechanism subdivisions includes one or more failure mechanism and each of the failure mechanisms includes one or more defect mechanisms), partitioning the failure mechanism subdivisions by area into partitions, pre-processing the device shapes in each partition, computing an initial average number of faults for each of the failure mechanisms and for each partition by numerical integration of an average probability of failure of each failure mechanism, (the numerical integration produces a list of defect sizes for each defect mechanism, and the computing of the initial average includes setting a maximum integration error limit, a maximum sample size for a population of each defect size, and a maximum number of allowable faults for each failure mechansim), and computing a final average number of faults for the integrated c

Abstract: The current invention provides a modification procedure that reduces errors in integrated circuits due to via shorts while at the same time avoiding the unnesting of the layout design and thereby permitting verification of the layout design by LVS testing tools. The current invention identifies if potentially shorting vias have electrically redundant paths and, if so, creates cloned cells of the original cell but void of the potentially shorting vias. The cloned cell is electrically comparable to the original cell. In addition, each instantiation of the original cell in the shapes data base is replaced with the cloned cell when electrical redundancy is present. Also, the number of vias removed can be minimized or maximized while, at the same time, all via electrical shorts are removed, depending on the design requirements.

Abstract: A method for manufacturing an integrated circuit having improved defect-limited yield. Each conductor on the integrated circuit is represented as an electrical element of a network, having branch voltages and currents. The width of the conductor is advantageously selected to have the minimum width necessary to produce signal levels that have sufficient noise margins. An integrated circuit conductive grid is thus realized having a reduced cross sectional area along a portion of various conductor element lengths, to reduce the risk that particles produced during manufacturing will result in bridging of adjacent conductor elements.

Abstract: A method of modifying a layout of a plurality of objects in accordance with a plurality of predetermined criteria is presented. An objective function is defined for measuring a location perturbation and a separation perturbation of the objects in the layout. A linear system is defined using linear constraints in terms of design rules and the objective function to describe separations between layout objects. The linear system is solved to simultaneously remove violations of the design rules, and shapes and positions of objects in the layout are modified in accordance with the solution of the linear system such that a total perturbation of the objects in the layout is reduced. A system for implementing the present invention is also presented.