Abstract: A method of chalcogenide device formation includes treatment of the surface upon which the chalcogenide material is deposited. The treatment reduces or eliminates native oxides and other contaminants from the surface, thereby increasing the adhesion of the chalcogenide layer to the treated surface, eliminating voids between the chalcogenide layer and deposition surface and reducing the degradation of chalcogenide material due to the migration of contaminants into the chalcogenide.

Abstract: An electronic device including a planar segmented contact. A method for forming the device includes depositing a first insulator on a substrate, forming an opening in the first insulator, disposing a conductive material in the opening where the conductive material defines two or more conductive regions, forming a second insulator over the conductive layer, removing a portion of the second insulator to expose less than all of the conductive regions, recessing at least one of the exposed conductive regions, forming a third insulator over the recessed conductive region, and planarizing to expose at least one of the non-recessed conductive regions without exposing a recessed conductive region. An electrically stimulable material may then be formed over an exposed non-recessed conductive region.

Abstract: A phase-change memory element exhibits a non-uniform temperature profile in the phase-change material, resulting in a non-uniform temperature profile. The non-uniform temperature profile causes non-uniform growth of a programmed volume, resulting in a gradual R-I characteristic. The phase-change material may be a chalcogenide material.

Abstract: A chalcogenide material and memory device exhibiting fast operation over an extended range of reset state resistances. Electrical devices containing the chalcogenide materials permit rapid transformations from the reset state to the set state for reset and set states having a high resistance ratio. The devices provide for high resistance contrast of memory states while preserving fast operational speeds. The chalcogenide materials include Ge, Sb and Te where the Ge and/or Te content is lean relative to Ge2Sb2Te5. In one embodiment, the concentration of Ge is between 11% and 22%, the concentration of Sb is between 22% and 65%, and the concentration of Te is between 28% and 55%. In a preferred embodiment, the concentration of Ge is between 15% and 18%, the concentration of Sb is between 32% and 35%, and the concentration of Te is between 48% and 51%.

Abstract: A chalcongenide material is proposed for programming the cross-connect transistor coupling interconnect lines of an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer in series with the select device or a phase change material. The matrix array may be used in a programmable logic device.

Abstract: A chalcogenide material is proposed for programming the cross-connect transistor coupling interconnect lines of an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer in series with the select device or a phase change material. The matrix array may be used in a programmable logic device.

Abstract: A chalcogenide material and chalcogenide memory device having less stringent requirements for formation, improved thermal stability and/or faster operation. The chalcogenide materials include materials comprising Ge, Sb and Te in which the Ge and/or Te content is lean relative to the commonly used Ge2Sb2Te5 chalcogenide composition. Electrical devices containing the instant chalcogenide materials show a rapid convergence of the set resistance during cycles of setting and resetting the device from its as-fabricated state, thus leading to a reduced or eliminated need to subject the device to post-fabrication electrical formation prior to end-use operation. Improved thermal stability is manifested in terms of prolonged stability of the resistance of the device at elevated temperatures, which leads to an inhibition of thermally induced setting of the reset state in the device. Significant improvements in the 10 year data retention temperature are demonstrated.

Abstract: A carbon containing layer may be formed between a pair of chalcogenide containing layers of a phase change memory. When the lower chalcogenide layer allows current to pass, a filament may be formed therein. The filament then localizes the electrical heating of the carbon containing layer, converting a relatively localized region to a lower conductivity region. This region then causes the localization of heating and current flow through the upper phase change material layer. In some embodiments, less phase change material may be required to change phase to form a phase change memory, reducing the current requirements of the resulting phase change memory.

Abstract: A memory may be implemented with a stable chalcogenide glass which is defined as a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to 200° C. for 30 minutes or less. Different states may be programmed by changing the threshold voltage of the material. The threshold voltage may be changed with pulses of different amplitude and/or different pulse fall times. Reading may be done using a reference level between the threshold voltages of the two different states. A separate access device is generally not needed.

Abstract: By using a resistive film as a shunt, the snapback exhibited when transitioning from the reset state or amorphous phase of a phase change material, may be reduced or avoided. The resistive film may be sufficiently resistive that it heats the phase change material and causes the appropriate phase transitions without requiring a dielectric breakdown of the phase change material.

Abstract: A phase change memory may be formed using a chalcogenide material that includes selenium. The inclusion of selenium improves the heat stability of the resulting memory device. The chalcogenide may also be a lean germanium composition.

Abstract: By using a resistive film as a shunt, the snapback exhibited when transitioning from the reset state or amorphous phase of a phase change material, may be reduced or avoided. The resistive film may be sufficiently resistive that it heats the phase change material and causes the appropriate phase transitions without requiring a dielectric breakdown of the phase change material.

Abstract: Briefly, in accordance with an embodiment of the invention, a phase change memory and a method to manufacture a phase change memory is provided. The phase change memory may include a memory material and a first tapered contact adjacent to the memory material. The phase change memory may further include a second tapered contact separated from the first tapered contact and adjacent to the memory material, wherein the first and second tapered contacts are adapted to provide a signal to the memory material.

Abstract: A non-volatile memory element includes a first interlayer insulation layer 11 having a first through-hole 11a, a second interlayer insulation layer 12 having a second through-hole 12a formed on the first interlayer insulation layer 11, a bottom electrode 13 provided in the first through-hole 11, recording layer 15 containing phase change material provided in the second through-hole 12, a top electrode 16 provided on the second interlayer insulation layer 12, and a thin-film insulation layer 14 formed between the bottom electrode 13 and the recording layer 15. In accordance with this invention, the diameter D1 of a bottom electrode 13 buried in a first through-hole 11a is smaller than the diameter D2 of a second through-hole 12a, thereby decreasing the thermal capacity of the bottom electrode 13.

Abstract: A lateral phase change memory includes a pair of electrodes separated by an insulating layer. The first electrode is formed in an opening in an insulating layer and is cup-shaped. The first electrode is covered by the insulating layer which is, in turn, covered by the second electrode. As a result, the spacing between the electrodes may be very precisely controlled and limited to very small dimensions. The electrodes are advantageously formed of the same material, prior to formation of the phase change material region.

Abstract: A chalcogenide material and chalcogenide memory device having less stringent requirements for formation, improved thermal stability and/or faster operation. The chalcogenide materials include materials comprising Ge, Sb and Te in which the Ge and/or Te content is lean relative to the commonly used Ge2Sb2Te5 chalcogenide composition. Electrical devices containing the instant chalcogenide materials show a rapid convergence of the set resistance during cycles of setting and resetting the device from its as-fabricated state, thus leading to a reduced or eliminated need to subject the device to post-fabrication electrical formation prior to end-use operation. Improved thermal stability is manifested in terms of prolonged stability of the resistance of the device at elevated temperatures, which leads to an inhibition of thermally induced setting of the reset state in the device. Significant improvements in the 10 year data retention temperature are demonstrated.

Abstract: A chalcogenide material and chalcogenide memory device exhibiting fast operation (short set pulse times) over an extended range of reset state resistances. Electrical devices containing the instant chalcogenide materials permit rapid transformations from the reset state to the set state for reset and set states having a high resistance ratio. The instant devices thus provide for high resistance contrast and improved readability of memory states while preserving fast operational speeds for the device. The chalcogenide materials include materials comprising Ge, Sb and Te in which the Ge and/or Te content is lean relative to the commonly used Ge2Sb2Te5 chalcogenide composition. In one embodiment, the atomic concentration of Ge is between 11% and 22%, the atomic concentration of Sb is between 22% and 65%, and the atomic concentration of Te is between 28% and 55%.

Abstract: A method of operating a programmable resistance memory array. The method comprises writing to all of the programmable resistance elements within the same row of the memory array at substantially the same time. The programmable resistance elements preferably include phase-change materials such as chalcogenides.

Abstract: Briefly, in accordance with an embodiment of the invention, a lateral phase change memory and a method to manufacture a phase change memory is provided. The method may include forming a conductor material over a substrate and patterning the conductor material to form two electrodes from the conductor material, wherein the two electrodes are separated by a sub-lithographic distance. The method may further include forming a phase change material between the two electrodes.

Abstract: A phase change memory may be formed of two vertically spaced layers of phase change material. An intervening dielectric may space the layers from one another along a substantial portion of their lateral extent. An opening may be provided in the intervening dielectric to allow the phase change layers to approach one another more closely. As a result, current density may be increased at this location, producing heating.