Abstract: A chalcongenide material is proposed for programming the cross-connect transistor coupling interconnect lines of an electrically programmable matrix array. Leakage may be reduced by optionally placing a thin insulating breakdown layer in series with the select device or a phase change material. The matrix array may be used in a programmable logic device.

Abstract: A carbon containing layer may be formed between a pair of chalcogenide containing layers of a phase change memory. When the lower chalcogenide layer allows current to pass, a filament may be formed therein. The filament then localizes the electrical heating of the carbon containing layer, converting a relatively localized region to a lower conductivity region. This region then causes the localization of heating and current flow through the upper phase change material layer. In some embodiments, less phase change material may be required to change phase to form a phase change memory, reducing the current requirements of the resulting phase change memory.

Abstract: A method of making an electrically programmable memory element, comprising: providing a conductive sidewall spacer; and forming a phase-change material in electrical communication with said conductive sidewall spacer.

Abstract: A memory element, a threshold switching element, or the series combination of a memory element and a threshold switching element may be used for coupling conductive lines in an electrically programmable matrix array. Leakage may be reduced by optionally placing a breakdown layer in series with the phase-change material and/or threshold switching material between the conductive lines. The matrix array may be used in a programmable logic device.

Abstract: A method of operating a programmable resistance memory array. The method comprises writing to all of the programmable resistance elements within the same row of the memory array at substantially the same time. The programmable resistance elements preferably include phase-change materials such as chalcogenides.

Abstract: A method of customizing an integrated circuit chip, comprising the steps of: providing an electronic circuit on said chip; providing a phase-change memory on the chip; storing information about said electronic circuit in the phase-change memory. A method of operating an optical display.

Abstract: Briefly, in accordance with an embodiment of the invention, a lateral phase change memory and a method to manufacture a phase change memory is provided. The method may include forming a conductor material over a substrate and patterning the conductor material to form two electrodes from the conductor material, wherein the two electrodes are separated by a sub-lithographic distance. The method may further include forming a phase change material between the two electrodes.

Abstract: By using a resistive film as a shunt, the snapback exhibited when transitioning from the reset state or amorphous phase of a phase change material, may be reduced or avoided. The resistive film may be sufficiently resistive that it heats the phase change material and causes the appropriate phase transitions without requiring a dielectric breakdown of the phase change material.

Abstract: A memory device including a plurality of memory cells, a plurality of insulated first regions of a first type of conductivity formed in a chip of semiconductor material, at least one second region of a second type of conductivity formed in each first region, a junction between each second region and the corresponding first region defining a unidirectional conduction access element for selecting a corresponding memory cell connected to the second region when forward biased, and at least one contact for contacting each first region; a plurality of access elements are formed in each first region, the access elements being grouped into at least one sub-set consisting of a plurality of adjacent access elements without interposition of any contact, and the memory device further includes means for forward biasing the access elements of each sub-set simultaneously.

Abstract: A parallel distributed processor comprises matrices of unit cells arranged in a stacked configuration. Each unit cell includes a chalcogenide body which may be set and reset to a plurality of values of a given physical property. Interconnections between the unit cells are established via the chalcogenide materials and the pattern and strength of the interconnections is determined by the set values of the chalcogenide. The processor is readily adapted to the construction of neural network computing systems.

Abstract: Digitizing apparatus for reproducing information from an image-bearing member, said apparatus including a wand removably mounted on a base station. The wand is adapted for independent operation to manually scan said image-bearing member or the wand can be secured to the base station for automatically scanning said image-bearing member.