Abstract: A transistor structure may include a first transistor beside a second transistor. The first transistor can include a first nanosheet oriented horizontally and forming a first channel, a second nanosheet oriented horizontally and forming a second channel, and a first gate structure disposed between and at least partly surrounding the first channel and the second channel. The second transistor can include a third nanosheet oriented horizontally and forming a third channel, a fourth nanosheet oriented horizontally and forming a fourth channel, and a second gate structure disposed between and at least partly surrounding the third channel and the fourth channel. The first nanosheet can be disposed above the third nanosheet, the third nanosheet is disposed above the second nanosheet, and the second nanosheet is disposed above the fourth nanosheet.

Abstract: A method includes forming a fin structure over a substrate, the fin structure including alternating first semiconductor layers and second semiconductor layers stacked along a vertical direction; forming a dummy gate structure over the fin structure; performing a plasma doping process to form source/drain regions in each second semiconductor layer adjacent the dummy gate structure, where a portion of each second semiconductor layer interposing between the source/drain regions defines a channel region; forming a dielectric layer over the fin structure; removing the dummy gate structure to form a gate trench in the dielectric layer; selectively removing the first semiconductor layers to form openings interleaved with the second semiconductor layers; depositing an inner spacer layer to partially fill the gate trench and the openings, wherein the inner spacer layer overlaps with the source/drain regions along the lateral direction; and forming a metal gate structure over the inner spacer layer.

Abstract: A method for fabricating and a structure comprising one or more transistors where a transistor includes one or more nanosheets formed based on one or more layers of a nanosheet material. A layer of shell material can at least partly surround the one or more nanosheets to form one or more channels of the transistor. A gate structure of the transistor can at least partly surround each of the one or more channels. The gate structure can include a gate dielectric disposed between the layer of the shell material and a gate metal of the gate structure for each of the nanosheets, where the shell material can include a charge carrier mobility that is greater than a charge carrier mobility of the nanosheet material.

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The method includes forming a first stack over a substrate including first dielectric layers and second dielectric layers alternately stacked on top of one another. The method includes replacing first, second, and third portions of the first stack with first, second, and third dielectric structures, respectively. The method includes replacing the first dielectric structure with a second stack including first semiconductor layers and second semiconductor layers alternately stacked on top of one another. The method includes removing a portion of the second dielectric structure and a portion of the third dielectric structure. The method includes exposing sidewalls of each of the second semiconductor layers. The method includes forming a pair of first epitaxial structures and a pair of second epitaxial structures in contact with the exposed sidewalls of a lower one and an upper one of the second semiconductor layers, respectively.

Abstract: Semiconductor devices and methods of manufacture are disclosed. The method includes forming a stack including a first pair of metal layers separated with a first dielectric layer and a second pair of metal layers separated with a second dielectric layer. The method includes separating the stack into a first portion of the first pair of metal layers and the first dielectric layer, a second portion of the first pair of metal layers and the first dielectric layer, a third portion of the second pair of metal layers and the second dielectric layer, and a fourth portion of the second pair of metal layers and the second dielectric layer. The method for fabricating semiconductor devices includes indenting, the first to fourth portions to form first to fourth recesses, respectively, and forming first to fourth transistors, respectively.

Abstract: Systems and methods for manufacturing two-dimensional (2D) gas channel for vertical transistors. The system can include a semiconductor device. The semiconductor device can include a channel structure surrounding a first dielectric core. The channel structure can include a first two-dimensional (2D) material and a second 2D material. The semiconductor device can include a source metal surrounding a first portion of the channel structure. The semiconductor device can include a drain metal surrounding a second portion of the channel structure. The semiconductor device can include a gate metal surrounding a third portion of the channel structure.

Abstract: Semiconductor devices and corresponding methods of manufacturing the same are disclosed. For example, a plurality of first semiconductor channels vertically spaced from one another and a plurality of second semiconductor channels vertically spaced from one another, wherein different materials are simultaneously epitaxial-grown for the first semiconductor channels and the second semiconductor channels, can be provided. The plurality of first semiconductor channels each have a first sidewall in contact with a dielectric structure and the plurality of second semiconductor channels each have a first sidewall in contact with the dielectric structure. Gate structures can be formed around at least a top surface, a bottom surface, and a second sidewall of the first and second semiconductor channels.

Abstract: A transistor structure is disclosed. The structure includes a first lower metal layer extending along one or more lateral directions. The structure includes a first upper metal layer in parallel with the first lower metal layer, wherein the first lower metal layer and the first upper metal layer are spaced from each other with a first isolation material. The structure includes a first channel extending from the first lower metal layer to the first upper metal layer. The structure includes a first dielectric spacer surrounded by the first channel and further by the first lower metal layer. The structure includes a second dielectric spacer also surrounded by the first channel and further by the first upper metal layer. The structure includes a first gate electrode surrounded by the first channel and vertically interposed between the first dielectric spacer and the second dielectric spacer.

Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The method includes forming a first stack over a substrate, including first dielectric layers and second dielectric layers alternately stacked on top of one another. The method includes replacing a first portion of the first stack with a second stack including first semiconductor layers and second semiconductor layers alternately stacked on top of one another. The method includes removing a second portion of the first stack to expose sidewalls of each of the second semiconductor layers, respectively. The method includes forming, through the removed second portion of the first stack, a pair of first epitaxial structures in contact with a lower one of the second semiconductor layers, respectively. The method includes forming, through the removed second portion of the first stack, a pair of second epitaxial structures in contact with an upper one of the second semiconductor layers, respectively.

Abstract: Systems and methods for manufacturing three-dimensional (3D) high density devices that are integrated with source and drain rails. The system can include a semiconductor device. The semiconductor device can include a conductor rail disposed below one or more transistors. The conductor rail can further include a first portion and a second portion arranged in parallel with each other. The semiconductor device can include a lower source/drain region disposed above the conductor rail. The semiconductor device can include a channel region disposed above the lower source/drain region. The semiconductor device can include an upper source/drain region disposed above the channel region. The lower source/drain region, the channel region, and the upper source/drain region each can include a semiconductor material. The semiconductor device can include a gate structure disposed around at least the channel region.

Abstract: Semiconductor devices and corresponding methods of manufacturing the same are disclosed. For example, a plurality of first semiconductor channels vertically spaced from one another and a plurality of second semiconductor channels vertically spaced from one another can be provided. The plurality of first semiconductor channels each have a first sidewall in contact with a first dielectric structure and the plurality of second semiconductor channels each have a first sidewall in contact with a second dielectric structure. A cavity can be formed between the first sidewalls of the plurality of first and second semiconductor channels. Gate structures can be formed around at least a top surface, a bottom surface, and a second sidewall of the first and second semiconductor channels.

Abstract: Semiconductor devices and corresponding methods of manufacturing the same are disclosed. For example, a plurality of first semiconductor channels vertically spaced from one another and a plurality of second semiconductor channels vertically spaced from one another can be provided. The plurality of first semiconductor channels each have a first sidewall in contact with a dielectric structure and the plurality of second semiconductor channels each have a first sidewall in contact with the dielectric structure. Gate structures can be formed around at least a top surface, a bottom surface, and a second sidewall of the first and second semiconductor channels.

Abstract: A method of processing a substrate includes forming a first layer stack on a substrate, the first layer stack including conductive layers and dielectric layers that alternate in the first layer stack. An opening is formed in the first layer stack, the opening extending through each of the conductive layers in the first layer stack such that sidewalls of each of the conductive layers are exposed within the opening. A second stack of layers is formed within the opening, the second stack of layers including channel layers of semiconductor material positioned in the second stack such that each channel layer contacts exposed sidewalls of a respective conductive layer of the first layer stack. Transistor channels are from the channel layers of the second stack such that each transistor channel extends between exposed sidewalls of a respective conductive layer within the opening.

Abstract: A semiconductor device includes a plurality of nano-channel field-effect transistor stacks positioned adjacent to each other such that source-drain regions are shared between adjacent nano-channel field-effect transistor stacks, each nano-channel field-effect transistor stack including at least two nano-channel field-effect transistors and corresponding source/drain regions vertically separated from each other.

Abstract: Aspects of the present disclosure provide a method of fabricating a semiconductor device. For example, the method can include providing a substrate. The substrate can include a first type region and a second type region. The method can also include forming a multilayer stack on the substrate. The multilayer stack can include alternate metal layers and dielectric layers. The method can also include forming first and second openings through the multilayer stack to uncover the first and second type regions, respectively. The method can also include forming first and second vertical channel structures within the first and second openings, respectively. Each of the first and second vertical channel structures can have source, gate and drain regions being in contact with vertical sidewalls of the metal layers of the multilayer stack uncovered by a respective one of the first and second openings.

Abstract: Aspects of the present disclosure provide a 3D semiconductor apparatus and a method for fabricating the same. The 3D semiconductor apparatus can include a first semiconductor device including sidewall structures of a first gate metal sandwiched by dielectric layers, a first epitaxially grown channel surrounded by the sidewall structures; a second semiconductor device formed on the same substrate adjacent to the first semiconductor device that includes sidewall structures of a second gate metal sandwiched by dielectric layers, a second epitaxially grown channel surrounded by the sidewall structures; a salicide layer formed between the first and second semiconductor devices and metallization contacting each of the S/D regions and the gate regions. The 3D semiconductor apparatus may include a P+ epitaxially grown channel formed on the same substrate adjacent to an N+ epitaxially grown channel, the P+ epitaxially grown channel separated from N+ epitaxially grown channel by a diffusion break.

Abstract: A method for marking a semiconductor substrate at the die level for providing unique authentication and serialization includes projecting a first pattern of actinic radiation onto a layer of photoresist on the substrate using mask-based photolithography, the first pattern defining semiconductor device structures and projecting a second pattern of actinic radiation onto the layer of photoresist using direct-write projection, the second pattern defining a unique wiring structure having a unique electrical signature.

Abstract: A semiconductor device may include a transistor structure. The transistor structure can include a first source/drain structure. The transistor structure can include a first channel structure disposed above the first source/drain structure. The transistor structure can include a second source/drain structure disposed above the first channel structure. A sidewall of a first portion of the first source/drain structure, a sidewall of the first channel structure, and a sidewall of the second source/drain structure can be vertically aligned with one another. The transistor structure can include a first metal electrode disposed around the sidewall of the first channel structure and the sidewall of the second source/drain structure.

Abstract: A method of microfabrication is provided. An initial stack of layers is formed over a semiconductor layer. The initial stack of layers can include a plurality of substacks separated from each other by one or more transition layers. One or more of the substacks include a sacrificial gate layer sandwiched between two first dielectric layers. Openings can be formed in the initial stack of layers so that the semiconductor layer is uncovered. The openings can be filled with vertical channel structures, where each vertical channel structure extends through a respective substack. The initial stack can be divided into separate stacks that include the vertical channel structures surrounded by the substacks and the transition layers. The one or more transition layers can be removed from the separate stacks to uncover transition points between neighboring vertical channel structures. Isolation structures can be formed at the transition points.

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack of insulating layers and interconnect layers that are positioned alternatingly over a substrate. The semiconductor device includes a channel structure extending from the substrate and further through the insulating layers and the interconnect layers. The channel structure includes a first channel section positioned over the substrate and coupled to a first group of the interconnect layers, and a second channel section positioned over the first channel section and coupled to a second group of the interconnect layers. The semiconductor device also includes a plurality of contact structures extending from and coupled to the interconnect layers in a staircase configuration such that each of the plurality of contact structures extends from a respective interconnect layer.