Patents by Inventor H. Jim Fulford

H. Jim Fulford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8575716
    Abstract: A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: November 5, 2013
    Assignee: Micron Technology, Inc.
    Inventors: James Mathew, Brett D. Lowe, Yunjun Ho, H. Jim Fulford, Jie Sun, Zhaoli Sun
  • Publication number: 20130249050
    Abstract: A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches.
    Type: Application
    Filed: May 14, 2013
    Publication date: September 26, 2013
    Applicant: Micron Technology, Inc.
    Inventors: James Mathew, Brett D. Lowe, Yunjun Ho, H. Jim Fulford, Jie Sun, Zhaoli Sun
  • Patent number: 8461016
    Abstract: A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: June 11, 2013
    Assignee: Micron Technology, Inc.
    Inventors: James Mathew, Brett D. Lowe, Yunjun Ho, H. Jim Fulford, Jie Sun, Zhaoli Sun
  • Publication number: 20130087883
    Abstract: A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches.
    Type: Application
    Filed: October 7, 2011
    Publication date: April 11, 2013
    Inventors: James Mathew, Brett D. Lowe, Yunjun Ho, H. Jim Fulford, Jie Sun, Zhaoli Sun
  • Patent number: 6979878
    Abstract: A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 ?. Silicon atoms and/or barrier atoms, such as nitrogen atoms, are then implanted ino regions of the active areas in close proximity to the trench isolation structure.
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: December 27, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, H. Jim Fulford, Derick J. Wristers
  • Patent number: 6911707
    Abstract: An ultrathin gate dielectric having a graded dielectric constant and a method for forming the same are provided. The gate dielectric is believed to allow enhanced performance of semiconductor devices including transistors and dual-gate memory cells. A thin nitrogen-containing oxide, preferably having a thickness of less than about 10 angstroms, is formed on a semiconductor substrate. A silicon nitride layer having a thickness of less than about 30 angstroms may be formed over the nitrogen-containing oxide. The oxide and nitride layers are annealed in ammonia and nitrous oxide ambients, and the nitride layer thickness is reduced using a flowing-gas etch process. The resulting two-layer gate dielectric is believed to provide increased capacitance as compared to a silicon dioxide dielectric while maintaining favorable interface properties with the underlying substrate. In an alternative embodiment, a different high dielectric constant material is substituted for the silicon nitride.
    Type: Grant
    Filed: December 9, 1998
    Date of Patent: June 28, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, Dim-Lee Kwong, H. Jim Fulford, Jr.
  • Patent number: 6746616
    Abstract: In one illustrative embodiment, a system is comprised of a semiconductor processing tool, an etcher, a metrology tool, and a controller. The semiconductor processing tool is capable of forming a process layer above a semiconducting substrate. The etcher is capable of removing at least a portion of the process layer. The metrology tool is capable of measuring a first depth of the etch at a first location in a first preselected region of the semiconducting substrate. The controller is capable of comparing the first depth to a desired depth, and varying the temperature of a subsequently processed semiconducting substrate in a region corresponding to the first preselected region in response to the first depth being different from the desired depth.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: June 8, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: H. Jim Fulford, Jeremy Lansford
  • Patent number: 6706631
    Abstract: A method of controlling the sheet resistance of metal silicide regions by controlling the salicide strip time is provided. In one illustrative embodiment, the method comprises forming a layer comprised of a refractory metal, determining a thickness of the layer of refractory metal, and converting a portion of the layer of refractory metal to a metal silicide. The method further comprises determining a duration of an etching process to be used to remove unreacted portions of the refractory metal layer based upon the determined thickness of the refractory metal layer, and performing the etching process for the determined duration.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: March 16, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventor: H. Jim Fulford
  • Patent number: 6661057
    Abstract: A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed aligned to a gate electrode. After forming an insulating layer adjacent the exposed surfaces of the gate electrode, conductive spacers are formed disposed overlying the LDD regions. These spacers are electrically isolated from the gate electrode by the insulating layer. Heavily doped source and drain (S/D) regions are formed which are aligned to the spacers and make electrical contact, for example through a salicide process, supplied to the conductive spacer, the gate electrode, and the S/D regions. The described structure advantageously supplies dynamic control of the channel region through dynamic, independent control of the LDD portions of the S/D regions.
    Type: Grant
    Filed: April 7, 1998
    Date of Patent: December 9, 2003
    Inventors: Robert Dawson, Mark I. Gardner, Frederick N. Hause, H. Jim Fulford, Jr., Mark W. Michael, Bradley T. Moore, Derick J. Wristers
  • Patent number: 6603180
    Abstract: A semiconductor device having a large-area silicide layer and fabrication method is provided. A semiconductor device, consistent with one embodiment of the invention, includes a silicon substrate, a gate insulating layer disposed over the silicon substrate, a gate electrode disposed over the gate insulating layer, and at least one active region disposed adjacent the gate electrode. Formed over the active region and in contact with the insulating layer is a silicide layer. The active region may, for example, be a source/drain region. The silicide layer generally has a surface area which is larger than that of conventional silicide layers. This, for example, reduces the resistance of the active regions of the semiconductor device and enhances device performance.
    Type: Grant
    Filed: November 28, 1997
    Date of Patent: August 5, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I Gardner, H. Jim Fulford
  • Patent number: 6558963
    Abstract: In general, the present invention is directed to a method of forming titanium nitride layers. In one illustrative embodiment, the method comprises forming a layer of titanium nitride by a chemical vapor deposition process, sensing a thickness of the layer of titanium nitride, and providing the sensed thickness of the layer of titanium nitride to a controller. The method further comprises determining at least one parameter of a plasma process to be performed on the layer of titanium nitride based upon the sensed thickness of the layer of titanium nitride and performing the plasma process comprised of the determined at least one parameter on the layer of titanium nitride.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: May 6, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Allen Lewis Evans, H. Jim Fulford
  • Patent number: 6552776
    Abstract: A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error increases. In this manner, when the lens error causes focusing variations that result in enlarged portions of the image pattern, the light filter reduces the light intensity transmitted to the enlarged portions of the image pattern. This, in turn, reduces the rate in which regions of the photoresist layer beneath the enlarged portions of the image pattern are rendered soluble to a subsequent developer. As a result, after the photoresist layer is developed, linewidth variations that otherwise result from the lens error are reduced due to the light filter.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: April 22, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Derick J. Wristers, Robert Dawson, H. Jim Fulford, Jr., Mark I. Gardner, Frederick N. Hause, Bradley T. Moore, Mark W. Michael
  • Publication number: 20030057432
    Abstract: An ultrathin gate dielectric having a graded dielectric constant and a method for forming the same are provided. The gate dielectric is believed to allow enhanced performance of semiconductor devices including transistors and dual-gate memory cells. A thin nitrogen-containing oxide, preferably having a thickness of less than about 10 angstroms, is formed on a semiconductor substrate. A silicon nitride layer having a thickness of less than about 30 angstroms may be formed over the nitrogen-containing oxide. The oxide and nitride layers are annealed in ammonia and nitrous oxide ambients, and the nitride layer thickness is reduced using a flowing-gas etch process. The resulting two-layer gate dielectric is believed to provide increased capacitance as compared to a silicon dioxide dielectric while maintaining favorable interface properties with the underlying substrate. In an alternative embodiment, a different high dielectric constant material is substituted for the silicon nitride.
    Type: Application
    Filed: December 9, 1998
    Publication date: March 27, 2003
    Inventors: MARK I. GARDNER, DIM-LEE KWONG, H. JIM FULFORD
  • Patent number: 6531364
    Abstract: A method is presented for forming a transistor wherein polysilicon is preferably deposited upon a dielectric-covered substrate to form a sacrificial polysilicon layer. The sacrificial polysilicon layer may then be reduced to a desired thickness. Thickness reduction of the sacrificial polysilicon layer is preferably undertaken by oxidizing a portion of the sacrificial polysilicon layer and then etching the oxidized portion. As an option, the sacrificial polysilicon layer may be heated such that it is recrystallized. The sacrificial polysilicon layer is preferably annealed in a nitrogen-bearing ambient such that it is converted to a gate dielectric layer that includes nitride. Polysilicon may be deposited upon the gate dielectric layer, and select portions of the polysilicon may be removed to form a gate conductor. LDD and source/drain areas may be formed adjacent to the gate conductor.
    Type: Grant
    Filed: August 5, 1998
    Date of Patent: March 11, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, H. Jim Fulford, Jr., Charles E. May
  • Patent number: 6500681
    Abstract: Disclosed herein is a method comprised of forming a metal layer above a structure layer on a workpiece, measuring a thickness of the metal layer, determining, based upon the measured thickness of the metal layer, at least one parameter of an etching process to be performed on the metal layer, and performing the etching process comprised of the determined parameter on the metal layer. Also disclosed is a system comprised of a deposition tool for forming a metal layer above a structure layer on a workpiece, a metrology tool for measuring a thickness of the metal layer, a controller for determining, based upon the measured thickness of the metal layer, at least one parameter of an etch process to be performed on the metal layer, and an etch tool adapted to perform an etch process comprised of the determined parameter on the metal layer.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: December 31, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Craig William Christian, H. Jim Fulford
  • Patent number: 6483157
    Abstract: A transistor fabrication process is provided which derives a benefit from having an asymmetrical LDD structure. A silicon-based substrate is provided. A gate oxide layer is grown across the substrate. The gate oxide layer may be incorporated with barrier atoms bonded to silicon or oxygen atoms. Suitable barrier atoms include nitrogen atoms which help reduce hot electron effects by blocking diffusion avenues of carriers (i.e., holes or electrons) from the drain-side junction, through the channel near the drain and into the gate oxide of the ensuing transistor. A polysilicon layer is then deposited across the gate oxide layer. Portions of the polysilicon layer and the oxide layer are then removed to form a gate conductor and gate oxide and to expose source-side and drain-side junctions within the substrate. A first dopant is implanted exclusively into only the source-side junction region. A second implant is then forwarded at a lower concentration into both junctions.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: November 19, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Patent number: 6454899
    Abstract: A method for filling a trench is provided. A wafer having at least a first layer formed thereon is provided. A trench is formed in the first layer. The depth of the trench is measured. A target thickness is determined based on the depth of the trench. A second layer of the target thickness is formed over the trench. A processing line includes a trench etch tool, a first metrology tool, a trench fill tool, and an automatic process controller. The trench etch tool is adapted to form a trench in a first layer on a wafer. The first metrology tool is adapted to measure the depth of the trench. The trench fill tool is adapted to form a second layer over the first layer based on an operating recipe. An automatic process controller is adapted to determine a target thickness based on the depth of the trench and modify the operating recipe of the trench fill tool based on the target thickness.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: September 24, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: William J. Campbell, H. Jim Fulford, Christopher H. Raeder, Craig W. Christian, Thomas Sonderman
  • Patent number: 6451657
    Abstract: A process is disclosed for fabricating a transistor having a channel length that is smaller than lengths resolvable using common photolithography techniques. A gate oxide layer is formed over a lightly doped semiconductor substrate. A gate conductor layer is then deposited over the gate oxide layer. The upper surface of the gate conductor layer includes a future conductor area laterally bounded by a spaced pair of target areas, wherein the lateral distance between the spaced pair of target areas is preferably chosen at the photolithography threshold. Nitrogen is implanted into the spaced pair of target areas to form a spaced pair of nitrogen bearing regions within the gate conductor layer, thereby defining a nitrogen free region in the gate conductor layer. A thermal anneal reduces the width of the nitrogen free region. A variable thickness oxide layer is then grown over the entire semiconductor topography and anisotropically etched to form an oxide mask over the reduced-width nitrogen free region.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: September 17, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, H. Jim Fulford, Jr., Charles E. May
  • Patent number: 6433400
    Abstract: A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a dielectric masking layer above a semiconductor substrate. An opening is then formed through the masking layer. A pair of dielectric spacers are formed upon the sidewalls of the masking layer within the opening. A trench is then etched in the semiconductor substrate between the dielectric spacers. A first dielectric layer is then thermally grown on the walls and base of the trench. A CVD oxide is deposited into the trench and processed such that the upper surface of the CVD oxide is commensurate with the substrate surface. Portions of the spacers are also removed such that the thickness of the spacers is between about 0 to 200 Å. The semiconductor topography is then exposed to a barrier-entrained gas and heated so that barrier atoms become incorporated in regions of the active areas in close proximity to the trench isolation structure.
    Type: Grant
    Filed: September 15, 1998
    Date of Patent: August 13, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, H. Jim Fulford, Derick J. Wristers
  • Patent number: 6420220
    Abstract: A method is provided for fabricating a semiconductor device, the method including forming a dielectric layer above a structure, forming a silicidable layer above the dielectric layer and forming a conductive layer above the silicidable layer. The method also includes forming a silicided layer by siliciding a portion of the conductive layer using at least a portion of the silicidable layer and forming a gate conductor having sides by patterning the silicided layer and the conductive layer.
    Type: Grant
    Filed: April 16, 1999
    Date of Patent: July 16, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, H. Jim Fulford, Charles E. May