Patents by Inventor H. Jim Fulford

H. Jim Fulford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12009355
    Abstract: Apparatuses, devices and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: June 11, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: H. Jim Fulford, Mark I. Gardner, Partha Mukhopadhyay
  • Patent number: 12002809
    Abstract: Aspects of the present disclosure provide a method of fabricating a semiconductor device including a plurality of vertically stacked transistors. For example, the method can include providing a vertical stack of alternating horizontal first and second layers, the second layers forming channels of the transistors. The method can further include uncovering the second layers. The method can further include forming a first shell on a first one of the uncovered second layers, the first shell and the first one of the uncovered second layers forming a first channel structure of a first one of the transistors.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: June 4, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Patent number: 12001147
    Abstract: Aspects of the present disclosure provide a method for improving overlay alignment of patterning by correcting wafer shape. For example, the method can include receiving a wafer having a working surface with at least partially-fabricated semiconductor devices, and a backside surface opposite to the working surface. The method can also include forming a first stressor film on the backside surface. The first stressor film can modify overlay alignment of the working surface in a first direction across the working surface of the wafer. The method can also include forming one or more first semiconductor structures on the working surface of the wafer. The first semiconductor structures are aligned in the first direction.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: June 4, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Daniel J. Fulford, Anthony R. Schepis, Mark I. Gardner, Anton J. Devilliers, H. Jim Fulford
  • Patent number: 11978735
    Abstract: A semiconductor device includes a substrate having a substrate surface, a transistor stack provided on the substrate surface and including a plurality of transistors stacked on each other along a vertical direction that is perpendicular to the substrate surface. Each transistor in the transistor stack includes a vertical channel structure extending along the vertical direction and having a first vertical sidewall and a second vertical sidewall opposite to the first vertical sidewall, and a ferroelectric gate structure in contact with the first vertical sidewall of the vertical channel structure; and a back gate structure provided on the substrate and in contact with the second vertical sidewall of the vertical channel structure of each respective transistor in the transistor stack.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: May 7, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Mark I. Gardner, Robert D. Clark, H. Jim Fulford
  • Publication number: 20240145576
    Abstract: A method includes forming a fin structure over a substrate, the fin structure including alternating first semiconductor layers and second semiconductor layers stacked along a vertical direction; forming a dummy gate structure over the fin structure; selectively depositing an outer spacer layer on the dummy gate structure; performing a plasma doping process to form source/drain regions in each second semiconductor layer adjacent the dummy gate structure, where a portion of each second semiconductor layer interposing between the source/drain regions defines a channel region; forming a dielectric layer over the fin structure; removing the dummy gate structure to form a gate trench in the dielectric layer; selectively removing the first semiconductor layers to form openings interleaved with the second semiconductor layers; and forming a metal gate structure to fill the gate trench and the openings.
    Type: Application
    Filed: October 27, 2022
    Publication date: May 2, 2024
    Applicant: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford, Partha Mukhopadhyay
  • Publication number: 20240145595
    Abstract: A semiconductor structure includes semiconductor layers stacked vertically over a substrate. The structure includes a gate structure interleaved with the semiconductor layers, where the gate structure wraps around a first end portion of each semiconductor layer. The structure includes dielectric layers stacked vertically over the substrate and interleaved with the semiconductor layers, where a first end portion of each dielectric layer is aligned with a second end portion of each semiconductor layer, which is laterally opposite to the first end portion of each semiconductor layer. The structure includes a metal contact extending vertically to contact the second end portion of each semiconductor layer.
    Type: Application
    Filed: October 27, 2022
    Publication date: May 2, 2024
    Applicant: Tokyo Electron Limited
    Inventors: H. Jim Fulford, Mark I. Gardner
  • Publication number: 20240120336
    Abstract: A transistor structure may include a first transistor beside a second transistor. The first transistor can include a first nanosheet oriented horizontally and forming a first channel, a second nanosheet oriented horizontally and forming a second channel, and a first gate structure disposed between and at least partly surrounding the first channel and the second channel. The second transistor can include a third nanosheet oriented horizontally and forming a third channel, a fourth nanosheet oriented horizontally and forming a fourth channel, and a second gate structure disposed between and at least partly surrounding the third channel and the fourth channel. The first nanosheet can be disposed above the third nanosheet, the third nanosheet is disposed above the second nanosheet, and the second nanosheet is disposed above the fourth nanosheet.
    Type: Application
    Filed: October 7, 2022
    Publication date: April 11, 2024
    Applicant: Tokyo Electron Limited
    Inventors: H. Jim Fulford, Mark I. Gardner
  • Publication number: 20240120407
    Abstract: A method includes forming a fin structure over a substrate, the fin structure including alternating first semiconductor layers and second semiconductor layers stacked along a vertical direction; forming a dummy gate structure over the fin structure; performing a plasma doping process to form source/drain regions in each second semiconductor layer adjacent the dummy gate structure, where a portion of each second semiconductor layer interposing between the source/drain regions defines a channel region; forming a dielectric layer over the fin structure; removing the dummy gate structure to form a gate trench in the dielectric layer; selectively removing the first semiconductor layers to form openings interleaved with the second semiconductor layers; depositing an inner spacer layer to partially fill the gate trench and the openings, wherein the inner spacer layer overlaps with the source/drain regions along the lateral direction; and forming a metal gate structure over the inner spacer layer.
    Type: Application
    Filed: October 7, 2022
    Publication date: April 11, 2024
    Applicant: Tokyo Electron Limited
    Inventors: H. Jim Fulford, Mark I. Gardner, Partha Mukhopadhyay
  • Publication number: 20240120375
    Abstract: A method for fabricating and a structure comprising one or more transistors where a transistor includes one or more nanosheets formed based on one or more layers of a nanosheet material. A layer of shell material can at least partly surround the one or more nanosheets to form one or more channels of the transistor. A gate structure of the transistor can at least partly surround each of the one or more channels. The gate structure can include a gate dielectric disposed between the layer of the shell material and a gate metal of the gate structure for each of the nanosheets, where the shell material can include a charge carrier mobility that is greater than a charge carrier mobility of the nanosheet material.
    Type: Application
    Filed: October 7, 2022
    Publication date: April 11, 2024
    Applicant: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Publication number: 20240113114
    Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The method includes forming a first stack over a substrate including first dielectric layers and second dielectric layers alternately stacked on top of one another. The method includes replacing first, second, and third portions of the first stack with first, second, and third dielectric structures, respectively. The method includes replacing the first dielectric structure with a second stack including first semiconductor layers and second semiconductor layers alternately stacked on top of one another. The method includes removing a portion of the second dielectric structure and a portion of the third dielectric structure. The method includes exposing sidewalls of each of the second semiconductor layers. The method includes forming a pair of first epitaxial structures and a pair of second epitaxial structures in contact with the exposed sidewalls of a lower one and an upper one of the second semiconductor layers, respectively.
    Type: Application
    Filed: September 22, 2022
    Publication date: April 4, 2024
    Applicant: Tokyo Electron Limited
    Inventors: H. Jim Fulford, Mark I. Gardner
  • Publication number: 20240105777
    Abstract: Semiconductor devices and methods of manufacture are disclosed. The method includes forming a stack including a first pair of metal layers separated with a first dielectric layer and a second pair of metal layers separated with a second dielectric layer. The method includes separating the stack into a first portion of the first pair of metal layers and the first dielectric layer, a second portion of the first pair of metal layers and the first dielectric layer, a third portion of the second pair of metal layers and the second dielectric layer, and a fourth portion of the second pair of metal layers and the second dielectric layer. The method for fabricating semiconductor devices includes indenting, the first to fourth portions to form first to fourth recesses, respectively, and forming first to fourth transistors, respectively.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 28, 2024
    Applicant: Tokyo Electron Limited
    Inventors: H. Jim Fulford, Mark I. Gardner
  • Patent number: 11942536
    Abstract: Systems and methods for manufacturing two-dimensional (2D) gas channel for vertical transistors. The system can include a semiconductor device. The semiconductor device can include a channel structure surrounding a first dielectric core. The channel structure can include a first two-dimensional (2D) material and a second 2D material. The semiconductor device can include a source metal surrounding a first portion of the channel structure. The semiconductor device can include a drain metal surrounding a second portion of the channel structure. The semiconductor device can include a gate metal surrounding a third portion of the channel structure.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: March 26, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Robert D. Clark, H. Jim Fulford, Mark I. Gardner
  • Publication number: 20240096708
    Abstract: Semiconductor devices and corresponding methods of manufacturing the same are disclosed. For example, a plurality of first semiconductor channels vertically spaced from one another and a plurality of second semiconductor channels vertically spaced from one another, wherein different materials are simultaneously epitaxial-grown for the first semiconductor channels and the second semiconductor channels, can be provided. The plurality of first semiconductor channels each have a first sidewall in contact with a dielectric structure and the plurality of second semiconductor channels each have a first sidewall in contact with the dielectric structure. Gate structures can be formed around at least a top surface, a bottom surface, and a second sidewall of the first and second semiconductor channels.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 21, 2024
    Applicant: Tokyo Electron Limited
    Inventors: H. Jim Fulford, Mark I. Gardner
  • Publication number: 20240079452
    Abstract: A transistor structure is disclosed. The structure includes a first lower metal layer extending along one or more lateral directions. The structure includes a first upper metal layer in parallel with the first lower metal layer, wherein the first lower metal layer and the first upper metal layer are spaced from each other with a first isolation material. The structure includes a first channel extending from the first lower metal layer to the first upper metal layer. The structure includes a first dielectric spacer surrounded by the first channel and further by the first lower metal layer. The structure includes a second dielectric spacer also surrounded by the first channel and further by the first upper metal layer. The structure includes a first gate electrode surrounded by the first channel and vertically interposed between the first dielectric spacer and the second dielectric spacer.
    Type: Application
    Filed: September 7, 2022
    Publication date: March 7, 2024
    Applicant: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Publication number: 20240079475
    Abstract: Semiconductor devices and corresponding methods of manufacture are disclosed. The method includes forming a first stack over a substrate, including first dielectric layers and second dielectric layers alternately stacked on top of one another. The method includes replacing a first portion of the first stack with a second stack including first semiconductor layers and second semiconductor layers alternately stacked on top of one another. The method includes removing a second portion of the first stack to expose sidewalls of each of the second semiconductor layers, respectively. The method includes forming, through the removed second portion of the first stack, a pair of first epitaxial structures in contact with a lower one of the second semiconductor layers, respectively. The method includes forming, through the removed second portion of the first stack, a pair of second epitaxial structures in contact with an upper one of the second semiconductor layers, respectively.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Applicant: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Publication number: 20240071871
    Abstract: Systems and methods for manufacturing three-dimensional (3D) high density devices that are integrated with source and drain rails. The system can include a semiconductor device. The semiconductor device can include a conductor rail disposed below one or more transistors. The conductor rail can further include a first portion and a second portion arranged in parallel with each other. The semiconductor device can include a lower source/drain region disposed above the conductor rail. The semiconductor device can include a channel region disposed above the lower source/drain region. The semiconductor device can include an upper source/drain region disposed above the channel region. The lower source/drain region, the channel region, and the upper source/drain region each can include a semiconductor material. The semiconductor device can include a gate structure disposed around at least the channel region.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Applicant: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Publication number: 20240063261
    Abstract: Semiconductor devices and corresponding methods of manufacturing the same are disclosed. For example, a plurality of first semiconductor channels vertically spaced from one another and a plurality of second semiconductor channels vertically spaced from one another can be provided. The plurality of first semiconductor channels each have a first sidewall in contact with a first dielectric structure and the plurality of second semiconductor channels each have a first sidewall in contact with a second dielectric structure. A cavity can be formed between the first sidewalls of the plurality of first and second semiconductor channels. Gate structures can be formed around at least a top surface, a bottom surface, and a second sidewall of the first and second semiconductor channels.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 22, 2024
    Applicant: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Publication number: 20240063220
    Abstract: Semiconductor devices and corresponding methods of manufacturing the same are disclosed. For example, a plurality of first semiconductor channels vertically spaced from one another and a plurality of second semiconductor channels vertically spaced from one another can be provided. The plurality of first semiconductor channels each have a first sidewall in contact with a dielectric structure and the plurality of second semiconductor channels each have a first sidewall in contact with the dielectric structure. Gate structures can be formed around at least a top surface, a bottom surface, and a second sidewall of the first and second semiconductor channels.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 22, 2024
    Applicant: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Patent number: 11908747
    Abstract: A method of processing a substrate includes forming a first layer stack on a substrate, the first layer stack including conductive layers and dielectric layers that alternate in the first layer stack. An opening is formed in the first layer stack, the opening extending through each of the conductive layers in the first layer stack such that sidewalls of each of the conductive layers are exposed within the opening. A second stack of layers is formed within the opening, the second stack of layers including channel layers of semiconductor material positioned in the second stack such that each channel layer contacts exposed sidewalls of a respective conductive layer of the first layer stack. Transistor channels are from the channel layers of the second stack such that each transistor channel extends between exposed sidewalls of a respective conductive layer within the opening.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: February 20, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Patent number: 11894378
    Abstract: A semiconductor device includes a plurality of nano-channel field-effect transistor stacks positioned adjacent to each other such that source-drain regions are shared between adjacent nano-channel field-effect transistor stacks, each nano-channel field-effect transistor stack including at least two nano-channel field-effect transistors and corresponding source/drain regions vertically separated from each other.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: February 6, 2024
    Assignee: Tokyo Electron Limited
    Inventors: H. Jim Fulford, Mark I. Gardner