Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack of channel layers positioned over a substrate, where the channel layers are spaced apart from one another. The semiconductor device includes source/drain (S/D) structures positioned at a first side and a second side of the stack of channel layers and in contact with the channel layers, where the first side is opposite to the second side. The semiconductor device includes gate dielectric layers arranged around the channel layers, and gate electrodes surrounding the gate dielectric layers and further extending from a third side and a fourth side of the stack of channel layers, where the third side is opposite to the fourth side. The semiconductor device further includes a seed layer positioned over the stack of channel layers.

Abstract: A method for fabricating semiconductor devices, may include forming a dielectric having a central portion with top and bottom surfaces thereof. A first sacrificial material and a second sacrificial material may be formed on the top and bottom surfaces, respectively, of the dielectric. End portions of the dielectric may be replaced with a first source/drain (S/D) metal and a second S/D metal. The central portion of the dielectric may be exposed at least by removing the first sacrificial material and second sacrificial material.

Abstract: Methods for the manufacture of semiconductor devices constructed with three-dimensional (3D) single crystal silicon nano sheets integrated with two-dimensional (2D) materials are disclosed. A device may include a semiconductor material and having a first end and a second end doped with a first polarity; a seed material wrapping around the semiconductor material; a two-dimensional (2D) material around the seed material; an active gate around the 2D material; and a source/drain structure in contact with the first end and the second end of the semiconductor material and in contact with the 2D material, wherein the source/drain structure is doped with a second polarity opposite to the first polarity.

Abstract: One or more 3D VFET structures with 2D material based channels using a wafer transfer technology and a metal first approach are disclosed. Transistor devices can be formed, where each transistor can include an elongate structure extending vertically from a first/source drain contact, a first end of the elongate structure in electrical contact with the first source/drain contact and a second end of the elongate structure in electrical contact with a second source/drain contact. The transistor can also include a channel that includes a 2D material layer extending along an external surface of the elongate structure and a gate structure including a high-k dielectric extending along the 2D material and a gate metal in contact with the high-k dielectric. The 2D material can laterally surround the elongate structure and the gate structure can surround the 2D material.

Abstract: One or more 3D transistor structures that use one or more 2D materials as transistor channels along with methods for fabricating the same are disclosed. A 3D transistor can include a source contact, a drain contact, a 2D material forming a channel between the source and drain contacts and surrounding a carrier nanosheet forming a first p-n junction with the source contact and a second p-n junction with the drain contact, and a gate structure comprising a gate dielectric and a gate contact contacting at least a portion of the channel between the first p-n junction and the second p-n junction. The source and drain contacts can comprise a doped semiconductor material and a channel having a first curved profile extending along the source contact and a second curved profile extending along the drain contact.

Abstract: Example implementations can include a semiconductor device with a first seed layer including a first material and having a planar structure, the first material having a two-dimensional structure, a first device layer including a second material and disposed over a first surface of the first seed layer, the second material having a crystallized structure, and a second device layer including the second material and disposed over a second surface of the first seed layer opposite to the first surface of the first seed layer.

Abstract: Systems and methods for manufacturing two-dimensional (2D) gas channel for vertical transistors. The system can include a semiconductor device. The semiconductor device can include a channel structure surrounding a first dielectric core. The channel structure can include a first two-dimensional (2D) material and a second 2D material. The semiconductor device can include a source metal surrounding a first portion of the channel structure. The semiconductor device can include a drain metal surrounding a second portion of the channel structure. The semiconductor device can include a gate metal surrounding a third portion of the channel structure.

Abstract: A semiconductor device includes a substrate with a working surface and a transistor formed in the substrate. The transistor includes a complex channel structure which is vertically arranged with respect to the working surface. The complex channel structure includes first and second source-drain (S-D) ends which are provided in a plane extending along the working surface to define an opening to a bounded region of the complex channel structure. The transistor also includes a gate dielectric layer formed on the complex channel structure within the bounded region, and a gate metal layer formed on the gate dielectric layer within the bounded region to form the transistor.

Abstract: A semiconductor device includes a transistor structure that includes a two-dimensional (2D) material around at least a dielectric structure. The transistor structure includes a first source/drain structure in contact with the first 2D material. The transistor structure includes a second source/drain structure in contact with the 2D material. The transistor structure includes a gate structure around at least the 2D material.

Abstract: A semiconductor device includes a stack of dynamic random access memory (DRAM) cell units over a substrate in a vertical direction perpendicular to a working surface of the substrate. Each DRAM cell unit includes a respective transistor, a respective capacitor and a respective bridge structure. Each bridge structure is configured to electrically couple the respective transistor to the respective capacitor. Each capacitor is elongated in a horizontal direction parallel to the working surface of the substrate.

Abstract: Methods for the manufacture of semiconductor devices with integrated two-dimensional (2D) materials are disclosed. Aspects can include forming a base structure comprising a seed material with a chemical element; forming source/drain contacts coupled to first and second portions of the base structure, respectively, wherein the source/drain contacts each have at least the chemical element; exposing a third portion of the base structure; selectively growing a 2D material at least coupled to the third portion of the base structure; and forming an active gate coupled to the 2D material.

Abstract: Methods for the manufacture of semiconductor devices constructed with two-dimensional (2D) materials and conductive oxides using three-dimensional (3D) nanosheets are disclosed. Aspects can include forming the stack of layers comprising a first layer of a semiconductive-behaving material separated from a base layer by a first layer of a first dielectric material and a first layer of a second dielectric material; a second layer of the semiconductive-behaving material separated from the first layer of the semiconductive-behaving material by a second layer of the second dielectric material; and a second layer of the second dielectric material formed on the second layer of the semiconductive-behaving material. Aspects include forming a metal contact coupled with the semiconductive-behaving material, forming a 2D material on the semiconductive-behaving material, forming a layer of a high-k dielectric material on the 2D material, and forming a gate metal on the high-k dielectric material.

Abstract: A method for manufacturing a semiconductor device is described. The method includes forming a first complementary field effect transistor. The first complementary field effect transistor has a first transistor of a first conductivity type, and a second transistor of a second conductivity above the first transistor. The first transistor includes a first gate electrode, a first channel above the first gate electrode, and first source and drain contacts above the first channel layer. The second transistor includes a second gate electrode, a second channel, and second source and drain contacts. The second channel is disposed between the second source and drain contacts and the second gate electrode. At least one of the first channel or the second channel includes a two-dimensional semiconductor material or an oxide semiconductor.

Abstract: Aspects of the present disclosure provide a method for optimizing wafer shape. For example, the method can include receiving a wafer having a working surface for one or more devices to be fabricated thereon and a backside surface opposite to the working surface, measuring the wafer to identify bow measurement of the wafer, and forming a stress-modification film on the backside surface of the wafer. The stress-modification film can be reactive to heat such that applied heat modifies an internal stress of the stress-modification film. The method can also include applying a pattern of heat onto the stress-modification film to modify the internal stress of the stress-modification film, the pattern of heat corresponding to the bow measurement.

Abstract: Technologies for making a complementary field effect transistor (CFET) semiconductor devices using selective source and drain epitaxial growth are described. The CFET semiconductor devices can be made using substantially uniformly-doped epitaxial layers to create self-aligned, selective epitaxial extensions that can be used as the source/drain regions in the transistor structures. Other embodiments are disclosed.

Abstract: Methods for the manufacture of semiconductor devices constructed with three-dimensional (3D) horizontal nano sheets with high mobility two-dimensional (2D) material channels are disclosed. Aspects can include forming a semiconductor material; selectively forming a seed material around the bridge; selectively forming a two-dimensional (2D) material around the seed material; forming an active gate around a central portion of the 2D material thereby exposing end portions of the 2D material; and growing source/drain structures coupled to the end portions of the 2D material, respectively.

Abstract: Methods for the manufacture of semiconductor devices constructed advanced three-dimensional (3D) device architectures using nanosheets with two-dimensional (2D) materials are disclosed. Aspects can include forming a dielectric layer; forming a conductive oxide layer on the dielectric layer; selectively forming a two-dimensional (2D) material around the conductive oxide layer; forming an active gate around the 2D material; and forming a first metal structure and a second metal structure, wherein the dielectric layer and conductive oxide layer extend between the first metal structure and the second metal structure.

Abstract: Aspects of the present disclosure provide a method for optimizing wafer shape. For example, the method can include receiving a wafer having a working surface for one or more devices to be fabricated thereon and a backside surface opposite to the working surface, measuring the wafer to identify bow measurement of the wafer, and forming a first stress-modification film on the backside surface. The first stress-modification film can be reactive to a first wavelength of light in that exposure to the first wavelength of light modifies an internal stress of the first stress-modification film. The method can further include exposing the first stress-modification film to a pattern of the first wavelength of light to modify the internal stress of the first stress-modification film. The pattern of the first wavelength of light corresponds to the bow measurement.

Abstract: Techniques herein include methods for fabricating three-dimensional (3D) logic or memory stack integrated with 3D metal routing. The methods can include stacking metal layers within existing 3D silicon stacks. A first portion can be masked while a second, uncovered portion is etched. Predetermined layers in a bottom portion (disposed closer to the substrate) of the multilayer stack can be replaced with a conductor. The second portion can be masked while the first portion is uncovered and processed. This can enable higher density 3D circuits by having multiple metal lines contained within a multilayer 3D nano-sheet. Advantageously, this facilitates easier connections for 3D logic and memory. Moreover, better speed performance can be achieved by having reduced distance for signals to travel to transistor connections.

Abstract: A method of microfabrication includes providing a substrate having a first layer including a first semiconductor material. A second layer of a second semiconductor material is formed over the first layer. The second layer is directionally etched using a mask to form independent core structures of the second semiconductor material on the first semiconductor material. A third layer of a first dielectric material is formed on an exposed surface of the first layer to cover a lower portion of a respective sidewall of each core structure. A shell structure is formed on an upper portion of a respective sidewall of each core structure to form shell structures including at least one semiconductor material. The core structures are removed such that each shell structure forms a vertical semiconductor structure extending vertically from the first layer and electrically isolated from the first semiconductor material by the first dielectric material.