Patents by Inventor H. Jim Fulford

H. Jim Fulford has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11688642
    Abstract: Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. The method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof, and attaching the first side to a carrier substrate. The method can further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure, and separating the carrier substrate from the first semiconductor structure. The method can further include cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet, and bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: June 27, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Anton J. Devilliers, Daniel J. Fulford, Anthony R. Schepis, Mark I. Gardner, H. Jim Fulford
  • Publication number: 20230200052
    Abstract: Apparatuses, devices, and methods for fabricating one or more vertically integrated single bit capacitor-based memory cells is disclosed. A single bit capacitor-based memory cell can include a vertically oriented transistor and a vertically oriented capacitor that is vertically integrated with the transistor, so as to form a memory cell. Aspects of the disclosure include process steps for forming the transistor and the capacitor, including a first metal part of a capacitor, a second metal part of a capacitor and an electrically insulating layer disposed between the two. The transistor and the capacitor also include an electrical contact between them and a layer that insulates the transistor from the base layer or the underlying substrate.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Applicant: Tokyo Electron Limited
    Inventors: H. Jim Fulford, Mark I. Gardner, Partha Mukhopadhyay
  • Publication number: 20230197715
    Abstract: A device including one or more transistors with nano sheets stacked along a vertical direction, and a method of fabricating the device are disclosed herein. In some embodiments, a device includes a transistor structure including at least a first dielectric nano sheet and a second dielectric nano sheet. The first dielectric nano sheet and the second dielectric nano sheet may extend parallel to a substrate. The second dielectric nano sheet may be disposed above the first dielectric nano sheet. The transistor may include a first source/drain structure coupled to a first end of the first dielectric nano sheet and a first end of the second dielectric nano sheet, and a second source/drain structure coupled to a second end of the first dielectric nano sheet and a second end of the second dielectric nano sheet.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Applicant: Tokyo Electron Limited
    Inventors: H. Jim Fulford, Mark I. Gardner
  • Publication number: 20230200066
    Abstract: Three-dimensional (3D) NAND memory structures and methods to manufacture 3D NAND memory structures are disclosed. A method includes forming a stack of layers that includes a first sub-stack for a transistor structure and a second sub-stack for a memory structure positioned on the first sub-stack. The second sub-stack includes at least one layer of conductive material and at least one layer of non-conductive material. The first sub-stack and the second sub-stack are separated by at least one non-conductive layer. The method includes forming a channel opening in the stack of layers, forming a gate dielectric in the channel opening, and providing a channel structure within the channel opening. The channel structure includes a semiconductive-behaving material and aligned with the transistor structure. The method includes providing a charge trap layer within the channel opening and aligned with the memory structure.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Publication number: 20230200065
    Abstract: Three-dimensional (3D) memory structures and methods to manufacture 3D memory structures are disclosed. A method includes forming a stack of layers including a first sub-stack for a first transistor structure, comprised of a first conductive layer, a gate layer, and a second source/drain layer. The stack of layers can include a second sub-stack for a memory structure positioned on the first sub-stack, the second sub-stack including at least one layer of conductive material and at least one layer of non-conductive material, and a third sub-stack for a second transistor structure. The method includes forming a channel opening in the stack of layers, providing a first channel structure within the channel opening, forming a memory dielectric layer in the channel opening and aligned with the memory structure, and providing a second channel structure in the channel opening in contact with the memory dielectric layer and aligned with the second transistor structure.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 22, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford, Partha Mukhopadhyay
  • Publication number: 20230187280
    Abstract: A semiconductor device includes a stack of layers defining a sidewall surface and comprising source and drain layers. A channel structure extends through the stack of layers, is oriented in a vertical direction perpendicular to a main surface of the stack of layers, and is configured to have a current flow path in the vertical direction. The channel structure includes a two-dimensional (2D) semiconductor material. A core structure is positioned inside and surrounded by the channel structure, and a gate structure surrounds at least part of the channel structure.
    Type: Application
    Filed: December 9, 2021
    Publication date: June 15, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Mark I. GARDNER, H. Jim FULFORD
  • Publication number: 20230189514
    Abstract: A semiconductor device includes a stack of layers, a vertical channel structure and vertical contact structures. The stack of layers defines a sidewall surface and includes terminal layers which include source, gate and drain layers. The vertical channel structure defines an inner axis that is substantially transverse to a main surface of the stack of layers. The vertical contact structures are each configured to electrically connect to a respective terminal layer. At least two vertical contact structures are in different radial positions relative to the inner axis.
    Type: Application
    Filed: December 9, 2021
    Publication date: June 15, 2023
    Applicant: Tokyo Electron Limited
    Inventors: H. Jim FULFORD, Mark I. GARDNER, Partha MUKHOPADHYAY
  • Publication number: 20230178599
    Abstract: Disclosed herein are related to a device including vertically placed semiconductor devices in a trench, and a method of fabricating the vertically placed semiconductor devices. In one aspect, a device includes a substrate including a trench defined by a first sidewall and a second sidewall facing each other along a first direction, and a floor between one end of the first sidewall and one end of the second sidewall. The device may include two or more vertical slots separated by vertical nano sheets extending upwards from the floor within the trench. In one aspect, the semiconductor devices can be formed in the two or more vertical slots. For example, source/drain structures, gate structures, and additional source/drain structures of vertical transistors can be formed in the two or more vertical slots.
    Type: Application
    Filed: December 8, 2021
    Publication date: June 8, 2023
    Applicant: Tokyo Electron Limited
    Inventors: H. Jim Fulford, Mark I. Gardner
  • Publication number: 20230178436
    Abstract: A method of microfabrication includes forming a stack of source/drain (S/D) contact structures over a substrate. The S/D contact structures are vertically separated. Gate contact structures are formed over the substrate and vertically separated. A first opening is formed so that middle portions of the S/D contact structures are removed while end portions of the S/D contact structures are positioned on opposing sides of the first opening. A layer stack is formed within the first opening, and includes channel structures stacked over the substrate, vertically separated and connected to respective end portions of the S/D contact structures. Second openings are formed, each uncovering a respective side surface of the layer stack and a respective side surface of at least one gate contact structure. Gate structures are formed in the second openings so that each gate structure is connected to a respective gate contact structure and a respective channel structure.
    Type: Application
    Filed: July 26, 2022
    Publication date: June 8, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Mark I. GARDNER, H. Jim FULFORD
  • Publication number: 20230161267
    Abstract: Aspects of the present disclosure provide a method for improving overlay alignment of patterning by correcting wafer shape. For example, the method can include receiving a wafer having a working surface with at least partially-fabricated semiconductor devices, and a backside surface opposite to the working surface. The method can also include forming a first stressor film on the backside surface. The first stressor film can modify overlay alignment of the working surface in a first direction across the working surface of the wafer. The method can also include forming one or more first semiconductor structures on the working surface of the wafer. The first semiconductor structures are aligned in the first direction.
    Type: Application
    Filed: August 16, 2022
    Publication date: May 25, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Daniel J. FULFORD, Anthony R. SCHEPIS, Mark I. GARDNER, Anton J. DEVILLIERS, H. Jim FULFORD
  • Patent number: 11652139
    Abstract: A semiconductor device includes a first universal device formed over a substrate, an isolation structure over the first universal device, and a second universal device over the isolation structure. The first universal device includes a first source/drain (S/D) region formed over the substrate, a first channel region over the first S/D region, a second S/D region over the first channel region. The second universal device includes a third S/D region positioned over the isolation structure, a second channel region over the third S/D region, a fourth S/D region over the second channel region. The first universal device is one of a first n-type transistor according to first applied bias voltages, and a first p-type transistor according to second applied bias voltages. The second universal device is one of a second n-type transistor according to third applied bias voltages, and a second p-type transistor according to fourth applied bias voltages.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: May 16, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Publication number: 20230147116
    Abstract: Methods for the manufacture of three-dimensional (3D) semiconductor devices are disclosed. Aspects can include forming a patterned first conductive source/drain structure of a transistor structure, forming a gate patterned conductive structure of the transistor structure separated from the first conductive source/drain structure by at least one dielectric layer, forming a patterned second conductive source/drain structure of the transistor structure separated from the gate patterned conductive structure by at least one dielectric layer, forming a transistor body opening extending through the transistor structure, forming a gate dielectric in the transistor body opening, and forming a material in the transistor body opening extending from the patterned first conductive source/drain structure to the patterned second conductive source/drain structure.
    Type: Application
    Filed: November 11, 2021
    Publication date: May 11, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford, Partha Mukhopadhyay
  • Patent number: 11640937
    Abstract: In a method for forming a semiconductor device, a plurality of conductive lines is formed as a part of a first wiring level of the semiconductor device. The first wiring level is positioned over a first level having a plurality of transistor devices. The plurality of conductive lines extends parallel to the first level. In addition, a programmable horizontal bridge is formed that extends parallel to the first level, and electrically connects a first conductive line and a second conductive line of the plurality of conductive lines in the first wiring level. The programmable horizontal bridge is formed based on a programmable material that changes phase between a conductive state and a non-conductive state according to a current pattern delivered to the programmable horizontal bridge.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: May 2, 2023
    Assignee: Tokyo Electron Limited
    Inventors: H. Jim Fulford, Mark I. Gardner, Anton J. deVilliers
  • Publication number: 20230128495
    Abstract: A semiconductor device includes a stack of transistors stacked over a base in a direction substantially perpendicular to a working surface of the base. Each transistor includes a respective channel structure, respective source/drain (S/D) regions positioned on ends of the respective channel structure, and a respective gate structure disposed all around the respective channel structure. Each channel structure includes a respective non-epitaxial compound semiconductor.
    Type: Application
    Filed: May 12, 2022
    Publication date: April 27, 2023
    Applicant: Tokyo Electron Limited
    Inventors: H. Jim FULFORD, Mark I. GARDNER, Partha MUKHOPADHYAY
  • Patent number: 11631671
    Abstract: A method of fabricating a semiconductor device is provided. An initial stack of layers is formed over a substrate. The initial stack alternates between a first material layer and a second material layer that has a different composition from the first material layer. The initial stack is divided into a first stack and a second stack. First GAA transistors are formed in the first stack by using the first material layers as respective channel regions for the first GAA transistors and using the second material layers as respective replacement gates for the first GAA transistors. Second GAA transistors are formed in the second stack by using the second material layers as respective channel regions for the second GAA transistors and using the first material layers as respective replacement gates for the second GAA transistors. The second GAA transistors are vertically offset from the first GAA transistors.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: April 18, 2023
    Assignee: Tokyo Electron Limited
    Inventors: H. Jim Fulford, Anton J. Devilliers, Mark I. Gardner, Daniel Chanemougame, Jeffrey Smith, Lars Liebmann, Subhadeep Kal
  • Publication number: 20230116857
    Abstract: The solution provides structures and fabrication steps for manufacturing a device that includes a core comprising a dielectric material extending vertically from a substrate and a vertical shell having a cross-section having a rounded portion. The vertical shell can include an epitaxially grown semiconductor material that at least partially surrounds the core and forms a channel of a transistor. The core can include a second vertical shell including a second epitaxially grown semiconductor material that at least partially surrounds the core and forms a second channel of the transistor.
    Type: Application
    Filed: August 4, 2022
    Publication date: April 13, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Publication number: 20230114024
    Abstract: One or more 3D transistor structures that use one or more 2D materials as transistor channels along with methods for fabricating the same are disclosed. A 3D transistor can include a first carrier nanosheet at least partially surrounded by a first 2D material and a second carrier nanosheet at least partially surrounded by a second 2D material. The transistor can include a first source/drain structure in electrical contact with a first end of the first 2D material and a first end of the second 2D material. The transistor can include a second source/drain structure in electrical contact with a second end of the first 2D material and a second end of the second 2D material. The transistor can include a gate structure at least partially surrounding the first 2D material and the second 2D material.
    Type: Application
    Filed: January 21, 2022
    Publication date: April 13, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Patent number: 11626329
    Abstract: A semiconductor device can include a pad layer including at least one pad structure having a core area surrounded by a peripheral area, and a transistor over the core area. The transistor includes a channel structure extending vertically and a gate structure all around a sidewall portion of the channel structure. The channel structure has a source region and a drain region on opposing ends of a vertical channel region. The channel structure is configured to be electrically coupled to the pad structure. The semiconductor device can further include a first vertical interconnect structure that contacts a top surface of the channel structure, a second vertical interconnect structure that contacts the peripheral area and is configured to be coupled to a bottom surface of the channel structure via the pad structure, and a third vertical interconnect structure that is positioned away from the channel structure and contacts the gate structure.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: April 11, 2023
    Assignee: Tokyo Electron Limited
    Inventors: H. Jim Fulford, Mark I. Gardner
  • Publication number: 20230108707
    Abstract: One or more 3D transistor structures that use one or more 2D materials as transistor channels along with methods for fabricating the same are disclosed. A 3D transistor can include a first carrier nanosheet at least partially surrounded by a first 2D material and a second carrier nanosheet at least partially surrounded by a second 2D material. The transistor can include a first source/drain structure in electrical contact with a first end of the first 2D material and a first end of the second 2D material. The transistor can include a second source/drain structure in electrical contact with a second end of the first 2D material and a second end of the second 2D material. The transistor can include a gate structure at least partially surrounding the first 2D material and the second 2D material.
    Type: Application
    Filed: January 18, 2022
    Publication date: April 6, 2023
    Applicant: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford
  • Patent number: 11610993
    Abstract: Aspects of the disclosure provide a method of forming a semiconductor apparatus including a first portion and a second portion. The first portion is formed on a first substrate and includes at least one first semiconductor device. The second portion is formed on a second substrate including a bulk substrate material and includes at least one second semiconductor device. A carrier substrate is attached to the second portion. The bulk substrate material is removed from the second substrate. The first portion and the second portion are bonded to form the semiconductor apparatus where the at least one second semiconductor device is stacked above the at least one first semiconductor device along a Z direction substantially perpendicular to a substrate plane of the first substrate. The at least one first semiconductor device and the at least one second semiconductor device are positioned between the carrier substrate and the first substrate.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: March 21, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Mark I. Gardner, H. Jim Fulford