Abstract: A method of forming an interposer includes providing a first interposer substrate including a first bulk material having a plurality of first through silicon vias (TSVs) extending through the first bulk material. Also provided is a second interposer substrate including a second bulk material having a plurality of second TSVs extending through the second bulk material, and a wiring plane formed on the second bulk material such that the wiring plane is electrically connected to at least one of the second TSVs. The method includes connecting a passive electrical device to at least one of the first and second interposer substrates. The first interposer substrate is joined to the second interposer substrate such that the passive electrical device is provided between the first and second interposer substrates and the wiring plane is provided as an interface wiring plane between the first and second bulk materials.

Abstract: Techniques herein include methods of forming higher density circuits by combining multiple substrates via stacking and bonding of individual substrates. High voltage and low voltage devices along with 3D NAND devises are fabricated on a first wafer, and high voltage and low voltage devices and/or memory are then fabricated on a second wafer and/or third wafer.

Abstract: A method of forming an interposer includes providing a first interposer substrate including a first bulk material having a plurality of first through silicon vias (TSVs) extending through the first bulk material. A second interposer substrate is provided and includes a second bulk material having a plurality of second TSVs extending through the second bulk material, and a wiring plane formed on the second bulk material such that the wiring plane is electrically connected to at least one of the second TSVs. The method further includes joining the first interposer substrate to the second interposer substrate such that the wiring plane is provided as an interface wiring plane between the first and second bulk materials which electrically connects at least one of the first TSVs to at least one of the second TSVs.

Abstract: Techniques herein include methods of forming circuits by combining multiple substrates. High voltage devices are fabricated on a first wafer, and low voltage devices and/or memory are then fabricated on a second wafer and/or third wafer.

Abstract: A charge trap field-effect transistor (FET) includes multiple layers of dielectric material defining a charge trapping layer. A p-doped (or n-doped) source region and a p-doped (or n-doped) drain region are connected via a nano-channel, the nano-channel being formed between the multiple layers of dielectric, thus forming a charge trap FET. A charge trap complimentary current field-effect transistor (CFET) includes multiple layers of dielectric material defining a charge trapping layer and includes a 3D charge trap PFET formed with p+ symmetrical source/drain region formed over a 3D charge trap NFET formed with n+ symmetrical source/drain region.

Abstract: A semiconductor device includes a first level having a plurality of transistor devices, and a first wiring level positioned over the first level. The first wiring level includes a plurality of conductive lines extending parallel to the first level, and one or more programmable horizontal bridges extending parallel to the first level. Each of the one or more programmable horizontal bridges electrically connects two respective conductive lines of the plurality of conductive lines in the first wiring level. The one or more programmable horizontal bridges include a programmable material having a modifiable resistivity in that the one or more programmable horizontal bridges change between being conductive and being non-conductive.

Abstract: A semiconductor device includes a first n-type transistor and a first p-type transistor that are positioned side by side over a substrate. The first n-type transistor includes a first n-type source/drain (S/D) region, a first n-type channel region, and a second n-type S/D region that are formed based on a first continuous channel structure extending along a horizontal direction parallel to the substrate. The first n-type channel region is positioned between the first n-type S/D region and the second n-type S/D region. The first p-type transistor includes a first p-type S/D region, a first p-type channel region, and a second p-type S/D region that are formed based on the first continuous channel structure. The first p-type channel region is positioned between the first p-type S/D region and the second p-type S/D region. The second n-type S/D region is in contact with the first p-type S/D region.

Abstract: A method of fabricating a semiconductor device is provided. An initial stack of layers is formed over a substrate. The initial stack alternates between a first material layer and a second material layer that has a different composition from the first material layer. The initial stack is divided into a first stack and a second stack. First GAA transistors are formed in the first stack by using the first material layers as respective channel regions for the first GAA transistors and using the second material layers as respective replacement gates for the first GAA transistors. Second GAA transistors are formed in the second stack by using the second material layers as respective channel regions for the second GAA transistors and using the first material layers as respective replacement gates for the second GAA transistors. The second GAA transistors are vertically offset from the first GAA transistors.

Abstract: A method of fabricating a semiconductor device includes forming a first stack of first transistor structures on a substrate, and forming a second stack of second transistor structures on the substrate adjacent to the first stack. The second stack is formed adjacent to the first stack such that stacked S/D regions at an end of the first stack are facing respective stacked S/D regions at an end of the second stack. A first pair of facing S/D regions of the first and second stack is connected by forming a connecting structure that extends in the horizontal direction to physically connect the first pair of facing S/D regions to each other. A second pair of facing S/D regions of the first and second stack is maintained as a separated pair of facing S/D regions which are physically separated from one another. First and second metal interconnect structures are connected to respective S/D regions in the second pair of facing S/D regions.

Abstract: Techniques herein include methods for fabricating high density logic and memory for advanced circuit architecture. The methods can enable higher density circuits to be produced at reduced cost. The methods can include growth of channel regions and S/D regions for NMOS devices using a first same nano-sheet in a nano-sheet stack. Similarly, the methods can include growth of channel regions and S/D regions for PMOS devices using a second same nano-sheet in the nano-sheet stack. The resulting 3D CMOS stack can include integrated channel and S/D regions.

Abstract: A semiconductor device includes an NMOS device formed on a first substrate bonded with a second substrate having a PMOS device formed thereon, with the bonding achieved by contacting a first wiring layer formed on the NMOS device with a second wiring layer formed on the PMOS device.

Abstract: Aspects of the disclosure provide a method of forming a semiconductor apparatus including a first portion and a second portion. The first portion is formed on a first substrate and includes at least one first semiconductor device. The second portion is formed on a second substrate including a bulk substrate material and includes at least one second semiconductor device. A carrier substrate is attached to the second portion. The bulk substrate material is removed from the second substrate. The first portion and the second portion are bonded to form the semiconductor apparatus where the at least one second semiconductor device is stacked above the at least one first semiconductor device along a Z direction substantially perpendicular to a substrate plane of the first substrate. The at least one first semiconductor device and the at least one second semiconductor device are positioned between the carrier substrate and the first substrate.

Abstract: Transistor/semiconductor devices and methods of forming transistor/semiconductor devices. The devices include a metal layer with dielectric isolation within existing 3D silicon stacks. Two different disposable materials within the 3D silicon stack are selectively removed later from other layers in the stack to become future metal layers and oxide layer respectively, to provide the metal line isolated in a vertical central portion of the stack.

Abstract: Techniques herein include methods for fabricating three-dimensional (3D) logic or memory stack integrated with 3D metal routing. The methods can include stacking metal layers within existing 3D silicon stacks. A first portion can be masked while a second, uncovered portion is etched. Predetermined layers in a bottom portion (disposed closer to the substrate) of the multilayer stack can be replaced with a conductor. The second portion can be masked while the first portion is uncovered and processed. This can enable higher density 3D circuits by having multiple metal lines contained within a multilayer 3D nano-sheet. Advantageously, this facilitates easier connections for 3D logic and memory. Moreover, better speed performance can be achieved by having reduced distance for signals to travel to transistor connections.

Abstract: Methods for 3D fabrication of source/drain regions in different stacks of 3D transistors in which multiple planes are fabricated simultaneously are described. The methods allow any sequence of 3D source/drains to be made to customize the logic layout for a given 3D logic circuit or design. Examples are described of forming a stacked SRAM device, a dual stacked SRAM device and a plurality of stacked inverters based on NMOS and PMOS field effect transistors.

Abstract: A charge trap tunnel field-effect transistor (TFET) includes multiple layers of dielectric material defining a charge trapping layer. A p-doped source/drain region and an n-doped source region are connected via a nano-channel, the nano-channel being formed between the multiple layers of dielectric, thus forming a charge trap TFET.

Abstract: In a method for forming a semiconductor device, a layer of logic devices is formed on a substrate. The layer of logic devices includes a stack of gate-all-around field-effect transistors (GAA-FETs) positioned over the substrate, where the stack of GAA-FETs includes a first layer of GAA-FETs stacked over a second layer of GAA-FETs. A first wiring layer is formed over the layer of logic devices, where the first wiring layer includes one or more metal routing levels. A memory stack is formed over the first wiring layer. The memory stack includes wordline layers and insulating layers that alternatingly arranged over the first wiring layer. A three-dimensional (3D) NAND memory device is formed in the memory stack. The 3D NAND memory device includes a channel structure that extends into the memory stack and further is coupled to the wordline layers of the memory stack.

Abstract: A method for forming a semiconductor device is provided. In the disclosed method, a stack is formed on a working surface of a substrate. The stack has alternating first layers and second layers positioned over the substrate. A separation structure is formed in the stack that separates the stack into a first region and a second region, where the separation structure extends in a first direction of the substrate. The second layers in the second region are further replaced with insulating layers, and the first layers in the second region are doped with a dopant.

Abstract: A semiconductor device is provided. The semiconductor device has a first transistor pair formed over a substrate. The first transistor pair includes a n-type transistor and a p-type transistor that are stacked over one another. The n-type transistor has a first channel region that includes one or more first nano-channels with a first stress. The one or more first nano-channels extend laterally along the substrate, are stacked over the substrate and spaced apart from one another. The p-type transistor has a second channel region that includes one or more second nano-channels with a second stress. The one or more second nano-channels extend laterally along the substrate, are stacked over the substrate and spaced apart from one another. Each of the one or more first nano-channels in the first channel region and each of the one or more second nano-channels in the second channel region are surrounded by a gate structure respectively.

Abstract: A semiconductor device includes a first transistor pair formed over a substrate. The first transistor pair includes a n-type transistor and a p-type transistor that are stacked over one another. The n-type transistor has a first channel region that includes one or more first nano-channels with a first bandgap value. The one or more first nano-channels extend laterally along the substrate, are stacked over the substrate and spaced apart from one another. The p-type transistor has a second channel region that includes one or more second nano-channels made of a compound material having a second bandgap value based on a predetermined material ratio of the compound material. The one or more second nano-channels extend laterally along the substrate, are stacked over the substrate and spaced apart from one another.