Abstract: A method of microfabrication is provided. An initial stack of layers is formed over a semiconductor layer. The initial stack of layers can include a plurality of substacks separated from each other by one or more transition layers. One or more of the substacks include a sacrificial gate layer sandwiched between two first dielectric layers. Openings can be formed in the initial stack of layers so that the semiconductor layer is uncovered. The openings can be filled with vertical channel structures, where each vertical channel structure extends through a respective substack. The initial stack can be divided into separate stacks that include the vertical channel structures surrounded by the substacks and the transition layers. The one or more transition layers can be removed from the separate stacks to uncover transition points between neighboring vertical channel structures. Isolation structures can be formed at the transition points.

Abstract: A semiconductor device includes a first transistor pair formed over a substrate. The first transistor pair includes a n-type transistor and a p-type transistor that are stacked over one another. The n-type transistor has a first channel region that includes one or more first nano-channels with a first bandgap value. The one or more first nano-channels extend laterally along the substrate, are stacked over the substrate and spaced apart from one another. The p-type transistor has a second channel region that includes one or more second nano-channels made of a compound material having a second bandgap value based on a predetermined material ratio of the compound material. The one or more second nano-channels extend laterally along the substrate, are stacked over the substrate and spaced apart from one another.

Abstract: Aspects of the present disclosure provide 3D semiconductor apparatus and a method for fabricating the same.

Abstract: A semiconductor device can include a pad layer including at least one pad structure having a core area surrounded by a peripheral area, and a transistor over the core area. The transistor includes a channel structure extending vertically and a gate structure all around a sidewall portion of the channel structure. The channel structure has a source region and a drain region on opposing ends of a vertical channel region. The channel structure is configured to be electrically coupled to the pad structure. The semiconductor device can further include a first vertical interconnect structure that contacts a top surface of the channel structure, a second vertical interconnect structure that contacts the peripheral area and is configured to be coupled to a bottom surface of the channel structure via the pad structure, and a third vertical interconnect structure that is positioned away from the channel structure and contacts the gate structure.

Abstract: Techniques herein include methods for fabricating high density logic and memory for advanced circuit architecture. The methods can include forming multilayer stacks on separate substrates and forming bonding films over the multilayer stacks, then contacting and bonding the bonding films to form a combined structure including each of the multilayer stacks. The method can be repeated to form additional combinations. In between iterations, transistor devices may be formed from the combined structures. Ionized atom implantation can facilitate cleavage of a substrate destined for growth of additional multilayers, wherein an anneal weakens the substrate at a predetermined penetration depth of the ionized atom implantation.

Abstract: In a method of forming a semiconductor device, an epitaxial layer stack is formed over a substrate. The epitaxial layer stack includes intermediate layers, one or more first nano layers and one or more second nano layers positioned below the one or more first nano layers. Trenches are formed in the epitaxial layer stack to separate the epitaxial layer stack into sub-stacks, the one of more first nano layers into first nano-channels, and the one or more second nano layers into second nano-channels. The intermediate layers are recessed so that one or more first nano-channels of the first nano-channels and one or more second nano-channels of the second nano-channels in each of the sub-stacks protrude from sidewalls of the intermediate layers. Bottom source/drain (S/D) regions are formed in the trenches to connect the second nano-channels. Top S/D regions are formed in the trenches to connect the first nano-channels.

Abstract: A method for marking a semiconductor substrate at the die level for providing unique authentication and serialization includes projecting a first pattern of actinic radiation onto a layer of photoresist on the substrate using mask-based photolithography, the first pattern defining semiconductor device structures and projecting a second pattern of actinic radiation onto the layer of photoresist using direct-write projection, the second pattern defining a unique wiring structure having a unique electrical signature.

Abstract: Transistor/semiconductor devices and methods of forming transistor/semiconductor devices. The devices include a metal layer with dielectric isolation within existing 3D silicon stacks. Two different disposable materials within the 3D silicon stack are selectively removed later from other layers in the stack to become future metal layers and oxide layer respectively, to provide the metal line isolated in a vertical central portion of the stack.

Abstract: A semiconductor device is provided. The semiconductor device can include a bottom substrate, a device plane over the bottom substrate, a dielectric layer over the device plane, localized substrates over the dielectric layer, and semiconductor devices over the localized substrates. The localized substrates can be separated from each other along a top surface of the bottom substrate. A method of microfabrication is provided. The method can include forming a target layer over a bottom substrate where the target layer includes one or more localized regions that include one or more semiconductor materials. The method can also include performing a thermal process to change crystal structures of the one or more localized regions of the target layer. The method can further include forming semiconductor devices over the localized regions of the target layer.

Abstract: Aspects of the present disclosure provide a vertical channel 3D semiconductor device sand a method for fabricating the same. The 3D semiconductor devices may have vertical channels of the same or different epitaxially grown doped materials. Sidewall structures are formed around each vertical channel by masking and etching material between the vertical channels. A dielectric layer in each of the sidewalls is etched down to the vertical channel and a gate electrode structure is formed in the opening. The gate electrode structure may include an interfacial oxide, a high-K layer and alternating metal layers. Local interconnects connect to the metal of the gate structure.

Abstract: A method of forming a semiconductor device is presented. A layer stack of alternating epitaxial materials including one or more layers is formed. The layer stack of alternating epitaxial materials into a first region of nano sheets and a second region of nano sheets is divided. A first field effect transistor on a working surface of a substrate using the nano sheets in the first region of nano sheets is formed. A stack of field effect transistors on the working surface of the substrate using the nano sheets in the second region of nano sheets is formed.

Abstract: Methods for 3D fabrication of source/drain regions in different stacks of 3D transistors in which multiple planes are fabricated simultaneously are described. The methods allow any sequence of 3D source/drains to be made to customize the logic layout for a given 3D logic circuit or design. Examples are described of forming a stacked SRAM device, a dual stacked SRAM device and a plurality of stacked inverters based on NMOS and PMOS field effect transistors.

Abstract: A method for marking a semiconductor substrate at the die level for providing unique authentication and serialization includes projecting a first pattern of actinic radiation onto a layer of photoresist on the substrate using mask-based photolithography, the first pattern defining semiconductor device structures and projecting a second pattern of actinic radiation onto the layer of photoresist using direct-write projection, the second pattern defining a unique wiring structure having a unique electrical signature.

Abstract: A semiconductor device is provided. The semiconductor device has a first transistor pair formed over a substrate. The first transistor pair includes a n-type transistor and a p-type transistor that are stacked over one another. The n-type transistor has a first channel region that includes one or more first nano-channels with a first stress. The one or more first nano-channels extend laterally along the substrate, are stacked over the substrate and spaced apart from one another. The p-type transistor has a second channel region that includes one or more second nano-channels with a second stress. The one or more second nano-channels extend laterally along the substrate, are stacked over the substrate and spaced apart from one another. Each of the one or more first nano-channels in the first channel region and each of the one or more second nano-channels in the second channel region are surrounded by a gate structure respectively.

Abstract: In a method for forming a semiconductor device, a plurality of conductive lines is formed as a part of a first wiring level of the semiconductor device. The first wiring level is positioned over a first level having a plurality of transistor devices. The plurality of conductive lines extends parallel to the first level. In addition, a programmable horizontal bridge is formed that extends parallel to the first level, and electrically connects a first conductive line and a second conductive line of the plurality of conductive lines in the first wiring level. The programmable horizontal bridge is formed based on a programmable material that changes phase between a conductive state and a non-conductive state according to a current pattern delivered to the programmable horizontal bridge.

Abstract: A method of forming transistor devices is described that includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of epitaxial film adaptable for forming channels of field effect transistors, depositing a first insulator layer on the first transistor plane, depositing a first layer of polycrystalline silicon on the first insulator layer, annealing the first layer of polycrystalline silicon using laser heating. The laser heating increases grain size of the first layer of polycrystalline silicon. The method further includes forming a second transistor plane on the first layer of polycrystalline silicon, the second transistor plane being adaptable for forming channels of field effect transistors, depositing a second insulator layer on the second transistor plane, depositing a second layer of polycrystalline silicon on the second insulator layer, and annealing the second layer of polycrystalline silicon using laser heating.

Abstract: A method of forming transistor devices includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of field effect transistors; depositing a first insulator layer on the first transistor plane; forming holes in the first insulator layer using a first etch mask; depositing a first layer of polycrystalline silicon on the first insulator layer, the first layer of polycrystalline filling the holes and covering the first insulator layer; and annealing the first layer of polycrystalline silicon using laser heating, the laser heating creating regions of single-crystal silicon. A top surface of the first transistor plane is a top surface of a stack of silicon formed by epitaxial growth.

Abstract: A method of forming an interposer includes providing a first interposer substrate including a first bulk material having a plurality of first through silicon vias (TSVs) extending through the first bulk material. Also provided is a second interposer substrate including a second bulk material having a plurality of second TSVs extending through the second bulk material, and a wiring plane formed on the second bulk material such that the wiring plane is electrically connected to at least one of the second TSVs. The method includes connecting a passive electrical device to at least one of the first and second interposer substrates. The first interposer substrate is joined to the second interposer substrate such that the passive electrical device is provided between the first and second interposer substrates and the wiring plane is provided as an interface wiring plane between the first and second bulk materials.

Abstract: Techniques herein include methods of forming higher density circuits by combining multiple substrates via stacking and bonding of individual substrates. High voltage and low voltage devices along with 3D NAND devises are fabricated on a first wafer, and high voltage and low voltage devices and/or memory are then fabricated on a second wafer and/or third wafer.

Abstract: A method of forming an interposer includes providing a first interposer substrate including a first bulk material having a plurality of first through silicon vias (TSVs) extending through the first bulk material. A second interposer substrate is provided and includes a second bulk material having a plurality of second TSVs extending through the second bulk material, and a wiring plane formed on the second bulk material such that the wiring plane is electrically connected to at least one of the second TSVs. The method further includes joining the first interposer substrate to the second interposer substrate such that the wiring plane is provided as an interface wiring plane between the first and second bulk materials which electrically connects at least one of the first TSVs to at least one of the second TSVs.