Abstract: Rapid thermal anneal with a gaseous dopant species for formation of a shallow lightly doped region is disclosed. In one embodiment of the invention, a method includes four steps. In the first step, at least one layer is applied over at least one gate over a semiconductor substrate. In the second step, an ion implantation is performed to form source and drain regions within the substrate. In the third step, the layers are removed. In the fourth step, a rapid thermal anneal with a gaseous dopant species is performed to form lightly doped regions within the substrate.

Abstract: A fabrication process and transistor are described in which a transistor having decreased susceptibility to punchthrough and increased resistance to impurity diffusion is formed. One or more argon doped silicon epitaxial layers are formed superjacent a semiconductor substrate. In a preferred dual layer embodiment, a first argon doped silicon epi layer is grown over a substrate, and a second argon doped epi layer, preferably having an argon concentration less than that in the first epi layer, is formed over the first epi layer. A transistor is formed in an active region of a well having a channel laterally bounded by source/drain regions located exclusively in the second epi layer. The lighter argon doping of the second epi layer accommodates current flow in the channel while acting as a barrier to impurity outdiffusion and inhibiting punchthrough. The more heavily doped first epi layer serves primarily as a barrier to outdiffusion of impurities from the bulk substrate.

Abstract: A partially formed semiconductor device includes a substrate, a first layer, a layer of polysilicon, and a grown layer of polysilicon. The first layer is positioned above at least a portion of the substrate. The layer of polysilicon is positioned above at least a portion of the first layer and has a first opening formed therein. The first opening has a first width that is defined by a plurality of sidewalls. The grown layer of polysilicon is positioned adjacent at least the plurality of sidewalls and the grown layer of polysilicon defines a second opening. The second opening has a second width with the second width being less than the first width. A method for partially forming a semiconductor device includes forming a process layer above at least a portion of a substrate. A layer of polysilicon is formed above at least a portion of the process layer. An opening is formed in the layer of polysilicon, and the opening has a first width that is defined by a plurality of sidewalls.

Abstract: A semiconductor device is provided and formed using self-aligned low-resistance gates within a metal-oxide semiconductor (MOS) process. A sacrificial dielectric gate structure is formed on a semiconductor substrate instead of a conventional gate dielectric/gate conductor stack. After forming junction regions within a semiconductor substrate, the gate structure is removed to form a trench within a dielectric formed above the substrate. A low-resistance gate material can then be arranged within the trench, i.e., in the region removed of the gate conductor. The gate material can take various forms, including a single layer or multiple metal and/or dielectric layers interposed throughout the as-filled trench. The gate formation occurs after high temperature cycles often associated with activating the previously implanted junctions or growing gate dielectrics. Thus, low-temperature metals such as copper or copper alloys can be used.

Abstract: An IGFET with a gate electrode and insulative spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, a gate insulator on the bottom surface, a gate electrode on the gate insulator, and insulative spacers between the gate electrode and the sidewalls.

Abstract: A method for forming an electrical contact is provided. A base layer having a conductive member is provided. An intermediate layer is formed over at least the conductive member. A photoresist layer is formed and patterned over at least a portion of the intermediate layer to define a contact patterning region above the conductive member. An amount of overlay between the contact patterning region and the conductive member is measured. A size of a contact opening is determined based on the amount of overlay. The contact opening of the determined size is formed in the intermediate layer. The contact opening communicates with the conductive member.

Abstract: An IGFET with elevated source and drain regions in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a lower gate level over a semiconductor substrate, wherein the lower gate level includes a top surface, a bottom surface and sloped opposing sidewalls, and the top surface has a substantially greater length than the bottom surface, and depositing a semiconducting layer on the lower gate level and on underlying source and drain regions of the semiconductor substrate to form an upper gate level on the lower gate level, an elevated source region on the underlying source region, and an elevated drain region on the underlying drain region. The elevated source and drain regions are separated from the lower gate level due to a retrograde slope of the sidewalls of the lower gate level, and the elevated source and drain regions are separated from the upper gate level due to a lack of step coverage in the semiconducting layer.

Abstract: An IGFET with metal spacers is disclosed. The IGFET includes a gate electrode on a gate insulator on a semiconductor substrate. Sidewall insulators are adjacent to opposing vertical edges of the gate electrode, and metal spacers are formed on the substrate and adjacent to the sidewall insulators. The metal spacers are electrically isolated from the gate electrode but contact portions of the drain and the source. Preferably, the metal spacers are adjacent to edges of the gate insulator beneath the sidewall insulators. The metal spacers are formed by depositing a metal layer over the substrate then applying an anisotropic etch. In one embodiment, the metal spacers contact lightly and heavily doped drain and source regions, thereby increasing the conductivity between the heavily doped drain and source regions and the channel underlying the gate electrode. The metal spacers can also provide low resistance drain and source contacts.

Abstract: A fabrication process and integrated circuit are provided in which a transistor having increased resistance to punchthrough and decreased channel capacitance is formed. A liner layer is formed within the active region of a transistor to minimize punchthrough. A barrier layer is then formed between the liner layer and the upper surface of the semiconductor substrate. The barrier layer preferably inhibits migration of the liner ions into the junction and channel regions of the transistors during subsequent processing steps. Such migration could deleteriously affect transistor function by, e.g., increasing the threshold voltage and thus decreasing the drive current. The barrier layer also preferably facilitates formation of shallow junctions. In an embodiment, the liner layer may include p-type ions such as boron and the barrier layer may include nitrogen implanted into the semiconductor substrate. Alternatively, the barrier layer may include nitrogen-incorporated epitaxially grown silicon.

Abstract: A method is provided for forming an integrated circuit having junctions of n-channel transistors dissimilar to junctions of p-channel transistors. First and second gate conductors are formed upon a gate dielectric on a semiconductor substrate. Spacers are formed on sidewalls of the first and second gate conductors. Portions of the spacers are subsequently removed such that the lateral width of each spacer is reduced to form residual spacers. The residual spacers may subsequently be removed, exposing sidewalls of the first and second gate conductors. At various stages of the method, n-type impurities may be implanted into the substrate, masked by the first gate conductor and any adjacent spacers or residual spacers. P-type impurites may also be implanted into the substrate, masked by the second gate conductor and any adjacent spacers or residual spacers.

Abstract: A method of forming integrated isolation regions and active regions includes first forming a plurality of dielectric layers upon a semiconductor substrate. Then, a patterned mask is applied to define portions of the dielectric layers that will remain to form isolation regions and to define portions of the dielectric layers that will be removed in an etch step to create voids to the surface of the semiconductor substrate. Subsequently, epitaxially growth is employed to form active regions within the voids that were previously formed. Transistors are then formed in and on the active regions and are subsequently interconnected to form an integrated circuit.

Abstract: A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes laterally displaced source/drain regions and channel regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. The first and second transistors have a common source/drain region. An isolation trench is formed through the common source/drain region and the trench is filled with a trench dielectric material such that the common source/drain region is divided into electrically isolated first and second source/drain regions whereby the first transistor is electrically isolated from the second transistor.

Abstract: A method for fabricating an integrated circuit is presented. In the method, a substrate is provided having a dielectric base layer formed thereupon. Source/drain trenches may be formed in the dielectric base layer. Source/drain structures containing metal may then be formed within the source/drain trenches. The upper surface of the dielectric base layer is then recessed a recession depth below upper surfaces of the source/drain structures. A gate trench is thus defined between upper portions of the source/drain structures extending above the upper surface of the dielectric base layer. A conductive channel layer is subsequently formed at least partially within the gate trench. A gate conductive layer may then be formed above the conductive channel layer and at least partially within the gate trench.

Abstract: An integrated circuit transistor and a method for making the same are provided. The transistor is resistant to junction shorts due to the overetch of local interconnect trenches. The transistor includes a source/drain region with a first junction and a second junction that is located deeper than the first junction in the portion of the active area susceptible to the overetch junction short phenomena. The second junction is established by ion implantation through a mask that is patterned to create an opening corresponding to the intersection of the layouts of the active area and the local interconnect trench. Using this method, the second junction is only established where needed to prevent shorting and does not impede transistor performance.

Abstract: Semiconductor devices having a gate electrode shared by two sets of active regions and methods of manufacture thereof are provided. In one embodiment, a first substrate is provided and a gate electrode is disposed over the first substrate. A second substrate is disposed over the gate electrode. A first set of active regions is disposed in portions of the first substrate adjacent the gate electrode and a second set of active regions is disposed above the gate electrode and adjacent the second substrate. The two sets of active regions may be coupled together or used separately.

Abstract: A semiconductor structure having multiple thicknesses of high-k gate dielectrics and a process of manufacture. In one embodiment, semiconductor structure is provided that includes a substrate, and a high permittivity layer is disposed on the substrate, the high permittivity layer having two or more areas with different thicknesses. A plurality of gate electrodes are disposed in the two or more areas on the high permittivity layer. In another embodiment, a process for constructing a semiconductor structure includes depositing a high permittivity layer on the substrate, the high permittivity layer having a first thickness. A first set of one or more gate electrodes are formed on the high permittivity layer having the first thickness. Selected portions of the high permittivity layer are then removed, whereby the high permittivity layer is reduced to a second thickness. Then a second set of gate electrodes are formed on the selected portions of the high permittivity layer having the second thickness.

Abstract: A semiconductor device having grown oxide spacers and a method for manufacturing such a semiconductor device is provided. In one embodiment of the invention, a gate electrode is formed over a substrate, and an oxidation-resistant layer is formed adjacent to the gate electrode. The gate electrode is oxidized to grow an oxide layer on the gate electrode extending over the oxidation-resistant layer. One or more spacers then is formed adjacent to the gate electrode using the oxide layer.

Abstract: An optical monitoring of electrical characteristics of devices in a semiconductor is performed during an anneal step to detect the time annealing is complete and activation occurs. A surface photovoltage measurement is made during annealing to monitor the charge state on the surface of a substrate wafer to determine when the substrate is fully annealed. The surface photovoltage measurement is monitored, the time of annealing is detected, and a selected over-anneal is controlled. The surface photovoltage (SPV) measurement is performed to determine a point at which a dopant or impurity such as boron or phosphorus is annealed in a silicon lattice. In some embodiments, the point of detection is used as a feedback signal in an RTA annealing system to adjust a bank of annealing lamps for annealing and activation uniformity control. The point of detection is also used to terminate the annealing process to minimize D.sub.t.

Abstract: A method is provided for fabricating a transistor, the method including forming a dielectric layer above a structure, forming a first polysilicon layer above the dielectric layer and forming a sacrificial region above the first polysilicon layer. The method also includes forming a second polysilicon layer above the first polysilicon layer and adjacent the sacrificial region. The method further includes removing the sacrificial region to form an opening in the second polysilicon layer, the opening having sidewalls, and forming dielectric spacers on the sidewalls of the opening. In addition, the method includes forming a gate dielectric within the opening above the first polysilicon layer and forming a gate conductor above the gate dielectric.

Abstract: Generally, the present invention relates to semiconductor devices having an oxide-nitride gate insulating layer and methods of manufacture thereof. Consistent with the present invention a semiconductor device is formed by forming a nitrogen bearing oxide layer over a substrate and forming a nitride layer over the nitrogen bearing oxide layer. The thickness of the nitride layer is reduced and the nitride layer is annealed in an NH.sub.3 bearing ambient. The NH.sub.3 anneal may, for example, be performed before or after or while reducing the thickness of the nitride layer. One or more of the gate electrodes may then be formed over the nitride layer using the nitrogen bearing oxide layer and the nitride layer to insulate the gate electrode(s) from the substrate. This technique can, for example, provide a highly reliable and scaled gate insulating layer.