Abstract: A method of fabricating integrated circuitry comprises forming a conductive line having opposing sidewalls over a semiconductor substrate. An insulating layer is then deposited. The insulating layer is etched proximate the line along at least a portion of at least one sidewall of the line. An insulating spacer forming layer is then deposited over the substrate and the line. It is anisotropically etched to form an insulating sidewall spacer. A method of forming a local interconnect comprises forming at least two transistor gates over a semiconductor substrate. A local interconnect layer is deposited to overlie at least one of the transistor gates and interconnect at least one source/drain region of one of the gates with semiconductor substrate material proximate another of the transistor gates.

Abstract: An SRAM cell is described which has a reduced cell area, and a reduced processing cost from conventional SRAM's. A fabrication process is described where self-aligned contacts to substrate active area and contact to a first layer of polysilicon are formed in one etch step. Electrical connection between the substrate and polysilicon is provided through a conductive layer coupled to the contacts. Self aligned contacts are fabricated to contact the active area.

Abstract: The invention encompasses methods of forming individual silicon-on-insulator layers having varying thicknesses within the individual layers. The invention also encompasses methods of forming transistor devices from silicon-on-insulator layers. Additionally, the invention encompasses semiconductor devices and assemblies utilizing silicon-on-insulator layers. The invention includes a method comprising: a) providing a substrate; b) providing an insulator layer over the substrate; c) providing a semiconductive layer over the insulator layer, the semiconductive layer having a first portion and a second portion; d) forming a depletion region within the semiconductive layer and proximate the insulator layer, the depletion region having a different thickness in the first portion than in the second portion; and f) etching the semiconductive layer to about the depletion region.

Abstract: A 4-T SRAM cell includes access transistors of a first type and cell (pull-up or pull-down) transistors of a second type. For example, the cell includes PMOS access transistors and NMOS pull-down transistors. The cell may also include leaky-junction or Schottky loads.

Abstract: An integrated circuit includes a substrate pump circuit developing an internal back-bias voltage on an output, and an external terminal adapted to receive an external back-bias voltage. A semiconductor substrate is coupled to the external terminal and to the output of the substrate pump circuit. The semiconductor substrate includes at least one transistor formed in the semiconductor substrate which has a first threshold voltage when the internal back-bias voltage is applied to the substrate. The at least one transistor has a second threshold voltage greater than the first threshold voltage when the external back-bias voltage is received on the external terminal.

Abstract: A 4-T SRAM cell includes access transistors of a first type and cell (pull-up or pull-down) transistors of a second type. For example, the cell includes PMOS access transistors and NMOS pull-down transistors. The cell may also include leaky-junction or Schottky loads.

Abstract: Semiconductor methods of forming self-aligned contact openings are described. In a preferred implementation, a conductor is formed over a substrate. A first layer of material is formed over the conductor A second layer of material is formed over the first layer of material. The first and second layer materials can be etchably different. Portion of the first and second layers are then removed to form a contact opening to the conductor. According to one aspect, the second layer material is removed at a slower rate than the rate at which first layer material is removed. According to another aspect, portions of such layers are removed at the same time. According to still another aspect of the invention, the second layer material comprises a sacrificial spun-on material.

Abstract: The present invention pertains to methods of forming integrated circuitry, methods of forming SRAM cells, and methods of reducing alpha particle inflicted damage to SRAM cells. Additionally, the present invention pertains to integrated circuitry. In one aspect, the invention includes a method comprising: a) forming at least one second conductivity type diffusion region beneath at least one of an SRAM cell pull-down device drain of a first conductivity type and an SRAM cell access device source of the first conductivity type; and b) not forming a second conductivity type diffusion region beneath at least one of a source of the SRAM cell pull-down device and a drain of the SRAM cell access device.

Abstract: Methods of forming conductive lines and insulative spacers thereover are described. In accordance with one aspect of the invention, a substrate is provided having a first area and a second area relative to which conductive lines are to be formed. A layer of conductive material is formed over the first and second substrate areas and a layer of insulative material is formed over the conductive material. In a preferred implementation, insulative material is removed from the second area and conductive lines are subsequently patterned and etched in both the first and second areas. In another preferred implementation, conductive lines are first patterned and etched with insulative material in the second area being subsequently removed. The patterned and etched conducted lines have respective sidewalls.

Abstract: The invention encompasses methods of forming individual silicon-on-insulator layers having varying thicknesses within the individual layers. The invention also encompasses methods of forming transistor devices from silicon-on-insulator layers. Additionally, the invention encompasses semiconductor devices and assemblies utilizing silicon-on-insulator layers. The invention includes a method comprising: a) providing a substrate; b) providing an insulator layer over the substrate; c) providing a semiconductive layer over the insulator layer, the semiconductive layer having a first portion and a second portion; d) forming a depletion region within the semiconductive layer and proximate the insulator layer, the depletion region having a different thickness in the first portion than in the second portion; and f) etching the semiconductive layer to about the depletion region.

Abstract: The invention encompasses methods of forming individual silicon-on-insulator layers having varying thicknesses within the individual layers. The invention also encompasses methods of forming transistor devices from silicon-on-insulator layers. Additionally, the invention encompasses semiconductor devices and assemblies utilizing silicon-on-insulator layers. The invention includes a method comprising: a) providing a substrate; b) providing an insulator layer over the substrate; c) providing a semiconductive layer over the insulator layer, the semiconductive layer having a first portion and a second portion; d) forming a depletion region within the semiconductive layer and proximate the insulator layer, the depletion region having a different thickness in the first portion than in the second portion; and f) etching the semiconductive layer to about the depletion region.

Abstract: The disclosure includes preferred semiconductor transistor devices utilizing thin film transistors, as well as preferred methods of forming such devices. Specifically, a bottom thin film transistor gate is formed having a top surface. An insulating filler is provided adjacent the thin film transistor gate to an elevation at least as high as the thin film transistor gate top surface, and subsequently levelled to provide generally planar insulating surfaces adjacent the thin film transistor gate. The planar insulating surfaces are substantially coplanar with the thin film transistor gate top surface. A planar semiconductor thin film is then formed over the thin film transistor gate and over the adjacent planar insulating surfaces. The thin film is doped to form source and drain regions of a thin film transistor which is bottom gated by the thin film transistor gate.

Abstract: A 4-T SRAM cell includes access transistors of a first type and cell (pull-up or pull-down) transistors of a second type. For example, the cell includes PMOS access transistors and NMOS pull-down transistors. The cell may also include leaky-junction or Schottky loads.

Abstract: Integrated circuitry fuse forming methods, integrated circuitry programming methods, and related integrated circuitry are described. In one implementation, a first layer comprising a first conductive material is formed over a substrate. A second layer comprising a second conductive material different from the first conductive material is formed over the first layer and in conductive connection therewith. A fuse area is formed by removing at least a portion of one of the first and second layers. In a preferred aspect, an assembly of layers comprising one layer disposed intermediate two conductive layers is provided. At least a portion of the one layer is removed from between the two layers to provide a void therebetween. In another aspect, programming circuitry is provided over a substrate upon which the assembly of layers is provided.

Abstract: The invention encompasses methods of forming individual silicon-on-insulator layers having varying thicknesses within the individual layers. The invention also encompasses methods of forming transistor devices from silicon-on-insulator layers. Additionally, the invention encompasses semiconductor devices and assemblies utilizing silicon-on-insulator layers. The invention includes a method comprising: a) providing a substrate; b) providing an insulator layer over the substrate; c) providing a semiconductive layer over the insulator layer, the semiconductive layer having a first portion and a second portion; d) forming a depletion region within the semiconductive layer and proximate the insulator layer, the depletion region having a different thickness in the first portion than in the second portion; and f) etching the semiconductive layer to about the depletion region.

Abstract: The present invention pertains to methods of forming integrated circuitry, methods of forming SRAM cells, and methods of reducing alpha particle inflicted damage to SRAM cells. Additionally, the present invention pertains to integrated circuitry. In one aspect, the invention includes a method which includes: a) forming at least one second conductivity type diffusion region beneath at least one of an SRAM cell pull-down device drain of a first conductivity type and an SRAM cell access device source of the first conductivity type; and b) not forming a second conductivity type diffusion region beneath at least one of a source of the SRAM cell pull-down device and a drain of the SRAM cell access device.

Abstract: Semiconductor methods of forming self-aligned contact openings are described. In a preferred implementation, a conductor is formed over a substrate. A first layer of material is formed over the conductor. A second layer of material is formed over the first layer of material. The first and second layer materials can be etchably different. Portions of the first and second layers are then removed to form a contact opening to the conductor. According to one aspect, the second layer material is removed at a slower rate than the rate at which first layer material is removed. According to another aspect, portions of such layers are removed at the same time. According to still another aspect of the invention, the second layer material comprises a sacrificial spun-on material.