Abstract: Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

Abstract: A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.

Abstract: A method and system for messaging, and more particularly archiving of messages in a distributed network of archiver nodes, by routing and grouping of the messages by customer, utilizing traditional recipient email addresses in SMTP is disclosed.

Abstract: A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.

Abstract: A SRAM device is provided having a plurality of memory cells. Each memory cell may include a plurality of transistors coupled in a cross-coupled inverter configuration. An NMOS transistor may be coupled to a body of the two PMOS transistors in the cross-coupled inverter configuration so as to apply a forward body bias to the PMOS transistors of the cross-coupled inverter configuration. A power control unit may control a supply voltage to each of the PMOS transistors as well as apply the switching signal to the NMOS transistor based on a STANDBY mode of the memory cell.

Abstract: A dynamic random access memory includes a cell having a circuit between a floating-body transistor and a bit line. Activation of the circuit is controlled to provide isolation between the floating body and bit-line voltage both during write operations and during times when the cell is unselected. The added isolation improves performance, for example, by reducing the need for gate-to-body coupling and the magnitude of voltage swings between the bit lines.

Abstract: Embodiments of the present invention provide a method, apparatus and system for dynamically adjusting one or more performance-related parameters of a processor core based on at least one operation parameter related to an operating condition of the processor core.

Abstract: High frequency signals and power carried in a main cable delivering the same to a device are insured continuance flow within the main cable through use of a shorting bypass bar assembly in the device that is activated to electrically connect input and output ports of the device whenever the cover of the device is removed for servicing, for insuring continuity of the signal and power flow through the main cable. The shorting bypass bar itself is electrically connected to ground whenever the cover of the device is installed and the shorting bypass bar is disabled.

Abstract: Compounds, pharmaceutical compositions and methods are provided that are useful in the treatment of inflammatory and immune-related diseases and conditions. In particular, the invention provides compounds which modulate the function and/or expression of proteins involved in atopic diseases, inflammatory conditions and cancer. The subject compounds are carboxylic acid derivatives.

Abstract: Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

Abstract: An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.

Abstract: A method is described that induced dielectric breakdown within a capacitor's dielectric material while driving a current through the capacitor. The current is specific to data that is being written into the capacitor. The method also involves reading the data by interpreting behavior of the capacitor that is determined by the capacitor's resistance, where, the capacitor's resistance is a consequence of the inducing and the driving.

Abstract: A method and apparatus for reducing power consumption in integrated memory devices is provided. Banks of memory cells may be individually put into “sleep” mode via respective “sleep” transistors.

Abstract: A one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. Access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.

Abstract: A manufacturing process modification is disclosed for producing a metal-insulator-metal (MIM) capacitor. The MIM capacitor may be used in memory cells, such as DRAMs, and may also be integrated into logic processing, such as for microprocessors. The processing used to generate the MIM capacitor is adaptable to current logic processing techniques. Other embodiments are described and claimed.

Abstract: A bias generator is provided that includes a central bias generator to provide a first bias voltage and a local bias generator to receive the first bias voltage and to provide a second bias voltage. The central bias generator may include a replica bias generator circuit substantially corresponding to the local bias generator.

Abstract: A highly efficient line transient protection circuit is provided for high power loads that are designed to operate through a high line transient. The transient protection circuit for high power loads is provided with a primary leg circuit, a load circuit and a secondary circuit. The load circuit may be a switching regulator circuit, a load circuit containing an oscillator, a push-pull circuit, a boost converter circuit, a buck converter circuit or the like. The transient protection circuit is provided with a simple driver circuit to turn on a bypass n-channel MOSFET. It operates at a higher efficiency; I.E., conduction losses are minimized during normal input voltage conditions. Furthermore, the transient protection circuit provides a programmable voltage clamp which is implemented through selecting zener diode VR1. The transient protection may be used to protect medium to large current circuits from line transients.

Abstract: In general, in one aspect, the disclosure describes a memory array including a plurality of memory cells arranged in rows and columns. Each memory cell includes a transistor having a floating body capable of storing a charge. A plurality of word lines and purge lines are interconnected to rows of memory cells. A plurality of bit lines are interconnected to columns of memory cells. Driving signals provided via the word lines, the purge lines, and the bit lines can cooperate to alter the charge of the floating body region in one or more of the memory cells.

Abstract: A method is described that comprises modulating the power consumption of an SRAM as a function of its usage at least by reaching, with help of a transistor, a voltage on a node within an operational amplifier's feedback loop. The voltage is beyond another voltage that the operational amplifier would drive the node to be without the help of the transistor. The voltage helps the feedback loop establish a voltage drop across a cell within the SRAM.