Patents by Inventor H. Tang

H. Tang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7001811
    Abstract: Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: February 21, 2006
    Assignee: Intel Corporation
    Inventors: Ali Keshavarzi, Stephen H. Tang, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien L. Lu, Vivek K. De
  • Patent number: 6992339
    Abstract: Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: January 31, 2006
    Assignee: Intel Corporation
    Inventors: Ali Keshavarzi, Stephen H. Tang, Dinesh Somasekhar, Fabrice Paillet, Muhammad M. Khellah, Yibin Ye, Shih-Lien L. Lu, Vivek K. De
  • Patent number: 6984308
    Abstract: This invention relates to an apparatus and method for the simultaneous and rapid determination of CoQ10 and CoQ10H2 concentrations in human samples using HPLC-EC. The electrochemical reactions are monitored at electrodes that measure the current produced by the reduction of the hydroquinone group of CoQ10 or by the oxidation of the hydroquinol group of CoQ10H2.
    Type: Grant
    Filed: March 4, 2002
    Date of Patent: January 10, 2006
    Assignee: Cincinnati Children's Hospital Research Foundation
    Inventors: Peter H. Tang, Ton de Grauw, Michael V. Miles
  • Patent number: 6975005
    Abstract: A current reference, which may be fabricated independently, on a die, as part of an integrated circuit, or a system, or in various other forms, is disclosed. The current reference may include a voltage source having a substantially temperature stable output voltage, a first semiconductor device biased by the substantially temperature stable output voltage to provide a first output current, and a second semiconductor device providing a second output current, wherein a reference current is provided approximately equal to the difference between the first and second output currents.
    Type: Grant
    Filed: October 20, 2003
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, Stephen H. Tang, Zachary Keer, Vivek K. De
  • Patent number: 6952376
    Abstract: An apparatus and method for generating a reference in a memory circuit are disclosed. At least two dummy bit-cells are used to generate a reference voltage. One cell has high value stored and the other has a low value stored. The cells are activated and discharged into respective bit-lines. The bit-lines are equalized during the discharge process to generate a reference that is approximately a mid point between a high value cell and a low value cell.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: October 4, 2005
    Assignee: Intel Corporation
    Inventors: Dinesh Somasekhar, Yibin Ye, Muhammad M. Khellah, Fabrice Paillet, Stephen H. Tang, Ali Keshavarzi, Shih-Lien Lu, Vivek K. De
  • Patent number: 6906973
    Abstract: Some embodiments provide pre-charge of a bit-line coupled to a memory cell to a reference voltage using a pre-charge device, discharge of the bit-line based on a value stored by the memory cell, injection during the discharge, of a first current into the bit-line using the pre-charge device, and injection, during the discharge, of a second current into a reference bit-line using a second pre-charge device. Also during the discharge, a difference is sensed between a voltage on the bit-line and a voltage on the reference bit-line.
    Type: Grant
    Filed: December 24, 2003
    Date of Patent: June 14, 2005
    Assignee: Intel Corporation
    Inventors: Dinesh Somasekhar, Yibin Ye, Muhammad M. Khellah, Fabrice Paillet, Stephen H. Tang, Ali Keshavarzi, Shih-Lien L. Lu, Vivek K. De
  • Patent number: 6893541
    Abstract: A DC magnetron sputter reactor for sputtering copper, its method of use, and shields and other parts promoting self-ionized plasma (SIP) sputtering, preferably at pressures below 5 milliTorr, preferably below 1 milliTorr. Also, a method of coating copper into a narrow and deep via or trench using SIP for a first copper layer. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. The SIP copper layer can act as a seed and nucleation layer for hole filling with conventional sputtering (PVD) or with electrochemical plating (ECP). For very high aspect-ratio holes, a copper seed layer is deposited by chemical vapor deposition (CVD) over the SIP copper nucleation layer, and PVD or ECP completes the hole filling. The copper seed layer may be deposited by a combination of SIP and high-density plasma sputtering. For very narrow holes, the CVD copper layer may fill the hole.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: May 17, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Tony P. Chiang, Yu D. Cong, Peijun Ding, Jianming Fu, Howard H. Tang, Anish Tolia
  • Patent number: 6870418
    Abstract: Embodiments of the present invention relate to current and/or voltage generation. The current and/or voltage generation may be process independent. Accordingly, variances in a manufacturing process will not substantially affect the ultimate current or voltage output from the circuit.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: March 22, 2005
    Assignee: Intel Corporation
    Inventors: Stephen H. Tang, Siva G. Narendra, Vivek K. De
  • Publication number: 20040224701
    Abstract: A wireless communication device (2) comprises a mobile unit for transmission and reception of voice calls through a mobile phone network having a user-accessible dial button (10) controlling a call activation switch, the unit being programmed to communicate with a first stored telephone number, which is typically that of a call centre able to provide assistance, on operation of said call activation switch, the unit also being provided with location determining functionality.
    Type: Application
    Filed: February 12, 2004
    Publication date: November 11, 2004
    Inventors: Jonathan P. Lewis-Evans, Michael T.H. Tang, Po Yang Chung, Ava Yat Lai Ku, Andrew Wing Nin Chan
  • Patent number: 6784722
    Abstract: A circuit is provided having a differential difference amplifier (DDA) having first and second inputs to receive a desired body bias signal, and a third input to receive a supply voltage, the DDA configured to generate an intermediate output signal, the intermediate output signal coupled to an output buffer generating an output signal having a desired gain, the DDA having a fourth input, to cause the output signal to reference to variations in the supply voltage.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: August 31, 2004
    Assignee: Intel Corporation
    Inventors: Stephen H. Tang, Dinesh Somasekhar, James W. Tschanz, Vivek K. De
  • Publication number: 20040139271
    Abstract: A multi-ported register comprises a Global Bit Line (GBL) to couple a gate to a data output line via an output transistor. A Local bit Line (LBL) couples the gate to a first register file cell and a second register file cell, said second register file cell disposed closer to the data output line than the first register file cell. At least one transistor in the first register file cell having a stronger drive current than the at least one transistor in the second register file cell. At least one of, the output transistor, the gate, and the first register file cell of a first bank have a stronger drive current than the corresponding output transistor, the gate and the first register file cell of a second bank said second bank being closer to the data output line.
    Type: Application
    Filed: December 27, 2002
    Publication date: July 15, 2004
    Inventors: Muhammad M. Khellah, Yibin Ye, Stephen H. Tang, Vivek De
  • Publication number: 20040080362
    Abstract: A current reference, which may be fabricated independently, on a die, as part of an integrated circuit, or a system, or in various other forms, is disclosed. The current reference may include a voltage source having a substantially temperature stable output voltage, a first semiconductor device biased by the substantially temperature stable output voltage to provide a first output current, and a second semiconductor device providing a second output current, wherein a reference current is provided approximately equal to the difference between the first and second output currents.
    Type: Application
    Filed: October 20, 2003
    Publication date: April 29, 2004
    Inventors: Siva G. Narendra, Stephen H. Tang, Zachary Keer, Vivek K. De
  • Publication number: 20040070440
    Abstract: According to some embodiments, a wide-range local bias generator provides a body bias voltage to transistors in an integrated circuit.
    Type: Application
    Filed: October 9, 2002
    Publication date: April 15, 2004
    Inventors: Stephen H. Tang, Dinesh Somasekhar, James W. Tschanz, Vivek K. De
  • Publication number: 20040058144
    Abstract: A pigmented curable composition adapted for decorating ceramic substrates (e.g., glass bottles) comprises curable organic binder and solid spherical particles (glass or polymer) having diameters of 10 to 50 microns for facilitating overprinting of additional layers. The preferred embodiment comprises: (a) reactive organic resin component in which epoxy groups comprise the major reactive functionality; (b) amino-functional curing agent; (c) blocked polyisocyanate; and (d) 5 to 35 percent solid spherical particles having diameters of 10 to 50 microns.
    Type: Application
    Filed: June 19, 2003
    Publication date: March 25, 2004
    Inventors: Robert H. Tang, Yingchao Zhang, Richard W. Morales, Alan E. Wang, Donald P. Hart
  • Patent number: 6710642
    Abstract: According to some embodiments, a bias generation circuit is provided.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: March 23, 2004
    Assignee: Intel Corporation
    Inventors: Stephen H. Tang, Siva G. Narendra, Vivek K. De
  • Patent number: 6693332
    Abstract: A current reference, which may be fabricated on a die, as part of an integrated circuit, or in various other forms, is disclosed. The current reference includes two current sources, both of which provide a substantially temperature stable output current, which may use a differencing circuit to provide a reference output current having a magnitude approximately equal to the difference between the magnitudes of the two substantially temperature stable output currents.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: February 17, 2004
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, Stephen H. Tang, Zachary Keer, Vivek K. De
  • Patent number: 6643199
    Abstract: For a memory cell, where an access transistor couples the memory cell to a local bit line, a pMOSFET essentially eliminates sub-threshold leakage current in the access transistor when the memory cell is not being read, and when the memory cell is being read, an additional pMOSFET essentially eliminates sub-threshold leakage current in the access transistor if the memory cell stores an information bit such that it does not discharge the local bit line. In this way, a half-keeper connected to the local bit line does not need to contend with sub-threshold leakage current.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: November 4, 2003
    Assignee: Intel Corporation
    Inventors: Stephen H. Tang, Steven K. Hsu, Vivek K. De, Shih-Lien L. Lu
  • Publication number: 20030124846
    Abstract: A DC magnetron sputter reactor for sputtering copper, its method of use, and shields and other parts promoting self-ionized plasma (SIP) sputtering, preferably at pressures below 5 milliTorr, preferably below 1 milliTorr. Also, a method of coating copper into a narrow and deep via or trench using SIP for a first copper layer. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. The SIP copper layer can act as a seed and nucleation layer for hole filling with conventional sputtering (PVD) or with electrochemical plating (ECP). For very high aspect-ratio holes, a copper seed layer is deposited by chemical vapor deposition (CVD) over the SIP copper nucleation layer, and PVD or ECP completes the hole filling. The copper seed layer may be deposited by a combination of SIP and high-density plasma sputtering. For very narrow holes, the CVD copper layer may fill the hole.
    Type: Application
    Filed: December 20, 2002
    Publication date: July 3, 2003
    Inventors: Tony P. Chiang, Yu D. Cong, Peijun Ding, Jianming Fu, Howard H. Tang, Anish Tolia
  • Patent number: 6582569
    Abstract: A DC magnetron sputter reactor for sputtering copper, its method of use, and shields and other parts promoting self-ionized plasma (SIP) sputtering, preferably at pressures below 5 milliTorr, preferably below 1 milliTorr. Also, a method of coating copper into a narrow and deep via or trench using SIP for a first copper layer. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. The SIP copper layer can act as a seed and nucleation layer for hole filling with conventional sputtering (PVD) or with electrochemical plating (ECP). For very high aspect-ratio holes, a copper seed layer is deposited by chemical vapor deposition (CVD) over the SIP copper nucleation layer, and PVD or ECP completes the hole filling. The copper seed layer may be deposited by a combination of SIP and high-density plasma sputtering. For very narrow holes, the CVD copper layer may fill the hole.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: June 24, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Tony P. Chiang, Yu D. Cong, Peijun Ding, Jianming Fu, Howard H. Tang, Anish Tolia
  • Publication number: 20030111698
    Abstract: A current reference, which may be fabricated on a die, as part of an integrated circuit, or in various other forms, is disclosed. The current reference includes two current sources, both of which provide a substantially temperature stable output current, which may use a differencing circuit to provide a reference output current having a magnitude approximately equal to the difference between the magnitudes of the two substantially temperature stable output currents.
    Type: Application
    Filed: December 19, 2001
    Publication date: June 19, 2003
    Applicant: Intel Corporation
    Inventors: Siva G. Narendra, Stephen H. Tang, Zachary Keer, Vivek K. De