Abstract: A multi-ported register comprises a Global Bit Line (GBL) to couple a gate to a data output line via an output transistor. A Local bit Line (LBL) couples the gate to a first register file cell and a second register file cell, said second register file cell disposed closer to the data output line than the first register file cell. At least one transistor in the first register file cell having a stronger drive current than the at least one transistor in the second register file cell. At least one of, the output transistor, the gate, and the first register file cell of a first bank have a stronger drive current than the corresponding output transistor, the gate and the first register file cell of a second bank said second bank being closer to the data output line.

Abstract: A method of programming a memory array is provided, including accessing a plurality of word lines of the memory array by providing a plurality of voltage steps sequentially after one another to the respective word lines, and accessing a plurality of bit lines of the memory array each time that a respective word line is accessed, to program a plurality of devices corresponding to individual word and bit lines that are simultaneously accessed, each device being programmed by breaking a dielectric layer of the device, accessing of the bit lines being sequenced such that only a single one of the devices is programmed at a time.

Abstract: A bias generator unit is provided that includes a central bias generator to provide a bias voltage, a local bias generator to receive the bias voltage and a reference voltage and to provide a forward body bias signal or a reverse body bias signal. The bias generator may include a charge pump to output (or provide) a reference voltage to a reference generator, which in turn provides reference signals to the central bias generator. As a result, the local bias generator may control the body bias signal provided by the local bias generator.

Abstract: A pigmented curable composition adapted for decorating ceramic substrates (e.g., glass bottles) comprises curable organic binder and solid spherical particles (glass or polymer) having diameters of 10 to 50 microns for facilitating overprinting of additional layers. The preferred embodiment comprises: (a) reactive organic resin component in which epoxy groups comprise the major reactive functionality; (b) amino-functional curing agent; (c) blocked polyisocyanate; and (d) 5 to 35 percent solid spherical particles having diameters of 10 to 50 microns.

Abstract: A two-transistor DRAM cell includes an NMOS device and a PMOS device coupled to the NMOS device.

Abstract: A two transistor memory cell includes a write transistor and a read transistor. When reading the memory cell, the read transistor is turned on, and a voltage develops on a read bit line.

Abstract: Crosspoint memory arrays utilizing one time programmable antifuse cells are disclosed.

Abstract: Apparatuses and methods for delaying thermal throttling of processor devices by decreasing threshold voltages are disclosed.

Abstract: A transistor may have degraded characteristics because of an overvoltage condition. The degraded characteristics may be sensed to determine that the transistor has previously been subjected to an overvoltage condition.

Abstract: Different embodiments of a one-time-programmable antifuse cell included. In one embodiment, a circuit is provided that includes an antifuse element, a high voltage device, and a sense circuit. The antifuse element has a voltage supply terminal to be at a sense voltage during sensing/reading and a higher programming voltage during programming. The sense circuit is configured to enable programming the antifuse element during programming and to sense the state of the antifuse element during sensing. The high voltage device is coupled between the antifuse element and the sense circuit to couple the antifuse element to the sense circuit during programming and sensing and to protectively shield the sense circuit from the higher programming voltage during programming.

Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

Abstract: A method and apparatus for a one-phase write to a one-transistor memory cell array. In one embodiment, the method includes a one-phase write to a selected wordline of a memory cell array. Once the wordline is selected, a logical zero value is stored within at least one memory cell of the selected wordline of the memory cell array. Simultaneously, a logical 0 value is stored within at least one memory cell of the selected wordline of the selected memory cell array. Other embodiments are described and claimed.

Abstract: A row of floating-body single transistor memory cells is written to in two phases.

Abstract: A system to write to a plurality of memory cells coupled to a word line, each of the plurality of memory cells comprising a transistor having a source, a drain, a body and a gate coupled to the word line. Some embodiments provide biasing of one or more of the plurality of memory cells in saturation to inject charge carriers into the body of the one or more of the plurality of memory cells, and biasing of each of the plurality of memory cells in accumulation to tunnel charge carriers from the body of each of the plurality of memory cells to the gate of each of the plurality of memory cells.

Abstract: Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.

Abstract: An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.

Abstract: Some embodiments provide a memory cell comprising a body region doped with charge carriers of a first type, a source region disposed in the body region and doped with charge carriers of a second type, and a drain region disposed in the body region and doped with charge carriers of the second type. According to some embodiments, the body region, the source region, and the drain region are oriented in a first direction, the body region and the source region form a first junction, and the body region and the drain region form a second junction. Moreover, a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased. Some embodiments further include a transistor oriented in a second direction, wherein the second direction is not parallel to the first direction.

Abstract: Embodiments relate to a Floating Body Dynamic Random Access Memory (FBDRAM). The FBDRAM utilizes a purge line to reset a FBDRAM cell, prior to writing data to the FBDRAM cell.

Abstract: Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

Abstract: This invention relates to an apparatus and method for the simultaneous and rapid determination of CoQ10 and CoQ10H2 concentrations in human samples using HPLC-EC. The electrochemical reactions are monitored at electrodes that measure the current produced by the reduction of the hydroquinone group of CoQ10 or by the oxidation of the hydroquinol group of CoQ10H2.