Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the

Abstract: Mandrel lines non-mandrel lines, and spacers are located in a structure having several layers. A spacer in the set of spacers comprises a structure formed above the top mask layer. A first trench is etched at a first location on a mandrel line through the top mask layer and stopping at the middle mask layer. A second trench is etched at a second location on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from the etching the trenches. Vias are formed in the first and second trenches. An air-gap is formed at a location of the spacer. The first via structure and a first portion of the bottom mask layer under the first via structure are removed and filled with a conductive metal.

Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 ?m2.

Abstract: Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions.

Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.

Abstract: A semi-floating gate transistor is implemented as a vertical FET built on a silicon substrate, wherein the source, drain, and channel are vertically aligned, on top of one another. Current flow between the source and the drain is influenced by a control gate and a semi-floating gate. Front side contacts can be made to each one of the source, drain, and control gate terminals of the vertical semi-floating gate transistor. The vertical semi-floating gate FET further includes a vertical tunneling FET and a vertical diode. Fabrication of the vertical semi-floating gate FET is compatible with conventional CMOS manufacturing processes, including a replacement metal gate process. Low-power operation allows the vertical semi-floating gate FET to provide a high current density compared with conventional planar devices.

Abstract: A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member.

Abstract: One illustrative method disclosed herein includes, among other things, forming a gate structure around a vertically oriented channel semiconductor structure above a bottom source/drain (S/D) region and below a top source/drain (S/D) region, the gate structure comprising a gate electrode and a gate insulation layer, a first portion of the gate insulation layer being positioned between the gate electrode and the vertically oriented channel semiconductor structure, removing second portion and third portions of the gate insulation layer while leaving at least some of the first portion in position to define a top spacer recess and a lower spacer recess and performing a common deposition process to simultaneously form a top spacer in the top spacer recess and a lower spacer in the lower spacer recess.

Abstract: A method for forming fins of a semiconductor device comprises forming a first hardmask on a substrate, a sacrificial layer on the first hardmask, and a second hardmask on the sacrificial layer. Portions of the second hardmask and the sacrificial layer are removed to form a mandrel. Spacers are formed adjacent to the sacrificial mandrel. A second sacrificial layer is deposited and portions of the second sacrificial layer are removed to expose portions of the spacers and the first hardmask. A first doped region and a second doped region are formed by annealing. The second hardmask and the sacrificial spacer are removed. Undoped portions of the sacrificial mandrel and the second sacrificial layer are removed to further expose portions of the first hardmask. Exposed portions of the first hardmask are removed to expose portions of the semiconductor substrate, and exposed portions of the semiconductor substrate are removed to form fins.

Abstract: A device is provided that includes a first die having a first alignment structure that includes a plurality of first transmission columns arranged in a pattern and a second die positioned on the first die, the second die having a second alignment structure that includes a plurality of second transmission columns arranged in the same pattern as the first transmission columns. The first and second transmission columns are each coplanar with a first surface and a second surface of the first and second die, respectively.

Abstract: A process for forming a conductive structure includes the formation of a self-aligned, inlaid conductive cap over a cobalt-based contact. The inlaid conductive cap is formed using a damascene process by depositing a conductive layer comprising tungsten or copper over a recessed cobalt-based contact, followed by a CMP step to remove excess portions of the conductive layer. The conductive cap can cooperate with a liner/barrier layer to form an effective barrier to cobalt migration and oxidation.

Abstract: A method for forming fins of a semiconductor device comprises forming a first hardmask on a substrate, a sacrificial layer on the first hardmask, and a second hardmask on the sacrificial layer. Portions of the second hardmask and the sacrificial layer are removed to form a mandrel. Spacers are formed adjacent to the sacrificial mandrel. A second sacrificial layer is deposited and portions of the second sacrificial layer are removed to expose portions of the spacers and the first hardmask. A first doped region and a second doped region are formed by annealing. The second hardmask and the sacrificial spacer are removed. Undoped portions of the sacrificial mandrel and the second sacrificial layer are removed to further expose portions of the first hardmask. Exposed portions of the first hardmask are removed to expose portions of the semiconductor substrate, and exposed portions of the semiconductor substrate are removed to form fins.

Abstract: A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral oxidation process. A temporary support structure is provided for the pillar during formation of the vacuum channel. Performance of the GAA vacuum channel transistor can be tuned by replacing air in the channel with other gases such as helium, neon, or argon. A threshold voltage of the GAA vacuum channel transistor can be adjusted by altering dopant concentrations of the silicon pillar from which the source and drain regions are formed.

Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the

Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.

Abstract: A method for producing self-aligned line end vias and the resulting device are provided. Embodiments include trench lines formed in a dielectric layer; each trench line including a pair of self aligned line end vias; and a high-density plasma (HDP) oxide, silicon carbide (SiC) or silicon carbon nitride (SiCNH) formed between each pair of self aligned line end vias, wherein the trench lines and self aligned line end vias are filled with a metal liner and metal.

Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by the

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical field effect transistors (VFETs) and methods of manufacture. The VFET includes: one or more vertical fin structures; a source region positioned at a first location on a top surface of the one or more vertical fin structures; a drain region positioned at a second location on the top surface of the one or more vertical fin structures at a predetermined distance away from the source region, along a length thereof; and a gate channel along the predetermined distance and in electrical contact with the source region and the drain region.

Abstract: A depth sensing multiple camera system is described that uses depth sensing cameras. In one example, the camera system includes a primary auto-focus camera to capture an image of a scene at a first focus distance, the primary camera having a fixed field of view through different focus distances, a secondary auto-focus camera to capture an image of the same scene at a second focus distance, the secondary camera having a fixed field of view through different focus distances, and a processor having a port coupled to the primary camera to receive images from the primary camera and also coupled to the secondary camera to receive images from the secondary camera and to determine a depth map for the captured primary camera image using the captured secondary camera image.