Patents by Inventor Hae Chan Park

Hae Chan Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190312057
    Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.
    Type: Application
    Filed: June 21, 2019
    Publication date: October 10, 2019
    Applicant: SK hynix Inc.
    Inventors: Hae Chan PARK, Jang Won KIM, Gong Hyun SA
  • Publication number: 20190291158
    Abstract: Provided is a press forming method for a composite material, which prevents a longitudinal section of the composite material from being exposed to outside. To this end, the method includes: cutting edges of the upper metal layer and the resin layer using a cutter such that the resin layer is cut relatively more than the upper metal layer; bending the upper metal layer toward the lower metal layer; and folding the lower metal layer by an angle of 180 degrees using a hemming die such that side surfaces of the upper metal layer and the resin layer are prevented from being exposed to outside.
    Type: Application
    Filed: March 21, 2018
    Publication date: September 26, 2019
    Inventor: Hae Chan PARK
  • Patent number: 10373971
    Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: August 6, 2019
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Jang Won Kim, Gong Hyun Sa
  • Patent number: 10296480
    Abstract: A data processing system includes a central processing unit (CPU), a control block configured to interface with the CPU, a cache memory configured to interface with the control block and arranged to be spaced from the CPU by a first distance, and a combined memory block configured to interface with the control block, arranged to be spaced from the CPU by a second distance larger than the first distance, and configured of a working memory and a storage memory. The combined memory block is configured of a plurality of stacked memory layers, each configured of a plurality of variable resistance memory cells. The working memory is allocated to one memory layer selected among the plurality of memory layers. The storage memory is allocated to remaining memory layers among the plurality of memory layers.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: May 21, 2019
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Sung Cheoul Kim, Tae Ho Kim
  • Publication number: 20190115425
    Abstract: A semiconductor device includes a stack structure located on a substrate and includes a first region, in which sacrificial layers and insulating layers are alternately stacked, and a second region, in which conductive layers and insulating layers are alternately stacked. The stack structure also includes a first slit insulating layer located at a boundary between the first region and the second region, wherein the first slit insulating layer penetrates the stack structure and extends in one direction. The stack structure further includes a plurality of slit insulating patterns located in the second region, wherein the plurality of slit insulating patterns penetrate the stack structure and are arranged along the one direction. At least one conductive layer among the conductive layers is bent between the first slit insulating layer and the slit insulating patterns.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 18, 2019
    Applicant: SK hynix Inc.
    Inventors: Hae Chan PARK, Jae Taek KIM
  • Patent number: 10177224
    Abstract: A semiconductor device includes a stack structure located on a substrate and includes a first region, in which sacrificial layers and insulating layers are alternately stacked, and a second region, in which conductive layers and insulating layers are alternately stacked. The stack structure also includes a first slit insulating layer located at a boundary between the first region and the second region, wherein the first slit insulating layer penetrates the stack structure and extends in one direction. The stack structure further includes a plurality of slit insulating patterns located in the second region, wherein the plurality of slit insulating patterns penetrate the stack structure and are arranged along the one direction. At least one conductive layer among the conductive layers is bent between the first slit insulating layer and the slit insulating patterns.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: January 8, 2019
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Jae Taek Kim
  • Publication number: 20180053779
    Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.
    Type: Application
    Filed: April 14, 2017
    Publication date: February 22, 2018
    Applicant: SK hynix Inc.
    Inventors: Hae Chan PARK, Jang Won KIM, Gong Hyun SA
  • Patent number: 9818481
    Abstract: A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell includes a data storage material and a non-silicon-substrate-based type bidirectional access device coupled in series, a path setting circuit coupled between the bit line and the word line, suitable for providing a program pulse toward the bit line or the word line based on a path control signal, a forward write command, and a reverse write command, and a control unit suitable for providing a write path control signal, a forward program command, and a reverse program command based on an external command signal.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: November 14, 2017
    Assignee: SK Hynix Inc.
    Inventors: Hae Chan Park, Myoung Sub Kim, Se Ho Lee, Seung Yun Lee
  • Publication number: 20170162262
    Abstract: A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell includes a data storage material and a non-silicon-substrate-based type bidirectional access device coupled in series, a path setting circuit coupled between the bit line and the word line, suitable for providing a program pulse toward the bit line or the word line based on a path control signal, a forward write command, and a reverse write command, and a control unit suitable for providing a write path control signal, a forward program command, and a reverse program command based on an external command signal.
    Type: Application
    Filed: February 16, 2017
    Publication date: June 8, 2017
    Inventors: Hae Chan PARK, Myoung Sub KIM, Se Ho LEE, Seung Yun LEE
  • Publication number: 20170148985
    Abstract: A semiconductor apparatus includes a variable resistor including a variable resistance layer, which is formed to surround on an inner surface of a resistive region, and an insert layer which is formed in the variable resistance layer and has a resistivity being different from that of the variable resistance layer.
    Type: Application
    Filed: February 2, 2017
    Publication date: May 25, 2017
    Inventor: Hae Chan PARK
  • Patent number: 9613690
    Abstract: A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell includes a data storage material and a non-silicon-substrate-based type bidirectional access device coupled in series, a path setting circuit coupled between the bit line and the word line, suitable for providing a program pulse toward the bit line or the word line based on a path control signal, a forward write command, and a reverse write command, and a control unit suitable for providing a write path control signal, a forward program command, and a reverse program command based on an external command signal.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: April 4, 2017
    Assignee: SK Hynix Inc.
    Inventors: Hae Chan Park, Myoung Sub Kim, Se Ho Lee, Seung Yun Lee
  • Patent number: 9601691
    Abstract: A semiconductor apparatus includes a variable resistor including a variable resistance layer, which is formed to surround on an inner surface of a resistive region, and an insert layer which is formed in the variable resistance layer and has a resistivity being different from that of the variable resistance layer.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: March 21, 2017
    Assignee: SK Hynix Inc.
    Inventor: Hae Chan Park
  • Patent number: 9552874
    Abstract: A combined memory block includes a first memory unit configured to store data and an additional memory unit that forms a stacked structure with the memory unit, wherein the memory unit and the storage unit together form multi-level cells having variable resistance in storing data.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: January 24, 2017
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hae Chan Park, Sung Cheoul Kim
  • Patent number: 9502646
    Abstract: A semiconductor integrated circuit device and a method of fabricating the same are disclosed. The semiconductor integrated circuit device includes a resistive layer and an encapsulation film formed to surround an outer wall of the resistive layer. The encapsulation film contains an oxygen absorbing ingredient.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: November 22, 2016
    Assignee: SK Hynix Inc.
    Inventors: Sang Chul Oh, Hae Chan Park, Se Ho Lee
  • Patent number: 9502651
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes an odd-numbered layer structure disposed over a substrate and including a plurality of first lines which extend in a first direction; an even-numbered layer structure disposed over the substrate and including a plurality of second lines which extend in a second direction crossing the first direction; and resistance variable layers interposed between the first lines, between the second lines, and between the first lines and the second lines, wherein the odd-numbered layer structure and the even-numbered layer structure are alternately stacked over the substrate.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: November 22, 2016
    Assignee: SK HYNIX INC.
    Inventor: Hae-Chan Park
  • Patent number: 9484390
    Abstract: A method for fabricating a semiconductor apparatus includes forming a diffusion barrier film on a semiconductor substrate, forming a first film on a semiconductor substrate including a common source region, forming a second film on the first film, forming a conductive film on the second film, patterning the conductive film and the second film, to form an active pattern, and patterning the first film and the semiconductor substrate using the active pattern as a mask, to form a pillar; and forming a gate electrode on an outer circumference of the pillar.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: November 1, 2016
    Assignee: SK Hynix Inc.
    Inventor: Hae Chan Park
  • Patent number: 9437295
    Abstract: A semiconductor memory apparatus and a temperature control method thereof are provided. The semiconductor memory apparatus includes a temperature adjustment unit suitable for adjusting a temperature of a memory cell, and a temperature control unit suitable for sensing a temperature of the temperature adjustment unit, comparing a sensed temperature with a reference temperature range, and controlling the temperature adjustment unit to adjust the temperature thereof within the reference temperature range based on a comparison result.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: September 6, 2016
    Assignee: SK Hynix Inc.
    Inventors: Seung Yun Lee, Hae Chan Park, Myoung Sub Kim, Se Ho Lee
  • Patent number: 9418736
    Abstract: A high voltage generating circuit for a resistive memory apparatus is provided. The high voltage generating circuit includes a capacitor spaced from a semiconductor substrate and electrically insulated from the semiconductor substrate. A switching device, which is electrically connected to the capacitor, is electrically insulated from the semiconductor substrate.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: August 16, 2016
    Assignee: SK Hynix Inc.
    Inventor: Hae Chan Park
  • Publication number: 20160210235
    Abstract: A data processing system includes a central processing unit (CPU), a control block configured to interface with the CPU, a cache memory configured to interface with the control block and arranged to be spaced from the CPU by a first distance, and a combined memory block configured to interface with the control block, arranged to be spaced from the CPU by a second distance larger than the first distance, and configured of a working memory and a storage memory. The combined memory block is configured of a plurality of stacked memory layers, each configured of a plurality of variable resistance memory cells. The working memory is allocated to one memory layer selected among the plurality of memory layers. The storage memory is allocated to remaining memory layers among the plurality of memory layers.
    Type: Application
    Filed: March 7, 2016
    Publication date: July 21, 2016
    Inventors: Hae Chan PARK, Sung Cheoul KIM, Tae Ho KIM
  • Patent number: 9385161
    Abstract: A semiconductor integrated circuit device having a reservoir capacitor and a method of manufacturing the same are provided. A first insulating layer is formed on a semiconductor substrate including a first region and a second region. A first conductive layer is formed on the first insulating layer, and a second insulating layer is formed on the first conductive layer. The second insulating layer is patterned to be left in a portion of the first region. A second conductive layer is formed on the second insulating layer and the first conductive layer. The second conductive layer is etched to expose a partial surface of the first conductive layer in the first region. The second conductive layer and the first conductive layer are etched to form a reservoir capacitor in the first region and form a gate in the second region.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: July 5, 2016
    Assignee: SK Hynix Inc.
    Inventor: Hae Chan Park