Patents by Inventor Hae Chan Park

Hae Chan Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11145594
    Abstract: The present technology relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another, a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack, a plurality of channel plugs vertically formed through the first stack and the second stack, and at least one dummy plug vertically formed through the second without passing through the first stack.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Jang Won Kim, Jae Taek Kim
  • Patent number: 11065662
    Abstract: Provided is a press forming method for a composite material, which prevents a longitudinal section of the composite material from being exposed to outside. To this end, the method includes: cutting edges of the upper metal layer and the resin layer using a cutter such that the resin layer is cut relatively more than the upper metal layer; bending the upper metal layer toward the lower metal layer; and folding the lower metal layer by an angle of 180 degrees using a hemming die such that side surfaces of the upper metal layer and the resin layer are prevented from being exposed to outside.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: July 20, 2021
    Assignee: OHSUNG DISPLAY CO, LTD.
    Inventor: Hae Chan Park
  • Publication number: 20210109413
    Abstract: The present disclosure relates to a display device. A display device according to an embodiment of the present inventive concept includes gate lines extending along a first direction, data lines extending along a second direction, pixels including pixel electrodes, each of the pixels including a transistor connected to a gate line and a data line, and a pixel electrode connected to the transistor, the pixels including a first pixel which includes a first pixel electrode connected to a first data line and is disposed in nth pixel row and mth pixel column, and a second pixel which includes a second pixel electrode connected to the first data line or a second data line disposed adjacent to the first data line and is disposed in (n+1)th pixel row and the mth pixel column. The first data line does not overlap the first pixel electrode and overlaps the second pixel electrode.
    Type: Application
    Filed: May 11, 2020
    Publication date: April 15, 2021
    Inventors: Se Hyun LEE, Hae Chan PARK, Min Gyeong SHIN, Hye Won JANG, Hak Sun CHANG
  • Publication number: 20210028105
    Abstract: The present technology relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first stack including first interlayer insulating layers and first conductive patterns which are alternately stacked with one another, a second stack including second interlayer insulating layers and second conductive patterns which are alternately stacked with one another on the first stack, a plurality of channel plugs vertically formed through the first stack and the second stack, and at least one dummy plug vertically formed through the second without passing through the first stack.
    Type: Application
    Filed: November 26, 2019
    Publication date: January 28, 2021
    Applicant: SK hynix Inc.
    Inventors: Hae Chan PARK, Jang Won KIM, Jae Taek KIM
  • Publication number: 20200348572
    Abstract: A liquid crystal display includes: a plurality of pixel electrodes; and a first data line and a second data line, each of the first data line and the second data line configured to transmit a data voltage and having substantially straight and angled portions. The first data line and the second data line are adjacent to each other in a first direction. The plurality of pixel electrodes includes: a first pixel electrode that overlaps both the first data line and the second data line; and a second pixel electrode disposed adjacent to the first pixel electrode in a second direction that intersects the first direction without overlapping the first data line and the second data line.
    Type: Application
    Filed: March 9, 2020
    Publication date: November 5, 2020
    Inventors: Se Hyun LEE, Hae Chan PARK, Min Gyeong SHIN, Hui Gyeong YUN, Seung Min LEE, Hak Sun CHANG
  • Patent number: 10811628
    Abstract: Provided is a press forming method for a composite material. A press forming method for a composite material including an upper metal member, a resin member, and a lower metal member, and including: producing the lower metal member having first and second coating films respectively bonded to upper and lower surfaces thereof; producing the composite material including the upper metal member, a first hot melt member, the resin member, a second hot melt member, and the lower metal member; cutting an area spaced inward a predetermined distance from a lengthwise edge of the composite material by using a T-cutter, such that only the lower metal member remains; removing the upper metal member, the first hot melt member, the resin member, and the second hot melt member that are located outside the cut area; and folding the lower metal member by an angle of 180 degrees by using a hemming die.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: October 20, 2020
    Assignee: OHSUNG DISPLAY CO., LTD.
    Inventors: Hae Chan Park, Sun Gyu Kim
  • Patent number: 10734407
    Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Jang Won Kim, Gong Hyun Sa
  • Publication number: 20200136084
    Abstract: Provided is a press forming method for a composite material. A press forming method for a composite material including an upper metal member, a resin member, and a lower metal member, and including: producing the lower metal member having first and second coating films respectively bonded to upper and lower surfaces thereof; producing the composite material including the upper metal member, a first hot melt member, the resin member, a second hot melt member, and the lower metal member; cutting an area spaced inward a predetermined distance from a lengthwise edge of the composite material by using a T-cutter, such that only the lower metal member remains; removing the upper metal member, the first hot melt member, the resin member, and the second hot melt member that are located outside the cut area; and folding the lower metal member by an angle of 180 degrees by using a hemming die.
    Type: Application
    Filed: March 8, 2019
    Publication date: April 30, 2020
    Inventors: Hae Chan PARK, Sun Gyu KIM
  • Patent number: 10566419
    Abstract: A semiconductor device includes a stack structure located on a substrate and includes a first region, in which sacrificial layers and insulating layers are alternately stacked, and a second region, in which conductive layers and insulating layers are alternately stacked. The stack structure also includes a first slit insulating layer located at a boundary between the first region and the second region, wherein the first slit insulating layer penetrates the stack structure and extends in one direction. The stack structure further includes a plurality of slit insulating patterns located in the second region, wherein the plurality of slit insulating patterns penetrate the stack structure and are arranged along the one direction. At least one conductive layer among the conductive layers is bent between the first slit insulating layer and the slit insulating patterns.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: February 18, 2020
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Jae Taek Kim
  • Publication number: 20190312057
    Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.
    Type: Application
    Filed: June 21, 2019
    Publication date: October 10, 2019
    Applicant: SK hynix Inc.
    Inventors: Hae Chan PARK, Jang Won KIM, Gong Hyun SA
  • Publication number: 20190291158
    Abstract: Provided is a press forming method for a composite material, which prevents a longitudinal section of the composite material from being exposed to outside. To this end, the method includes: cutting edges of the upper metal layer and the resin layer using a cutter such that the resin layer is cut relatively more than the upper metal layer; bending the upper metal layer toward the lower metal layer; and folding the lower metal layer by an angle of 180 degrees using a hemming die such that side surfaces of the upper metal layer and the resin layer are prevented from being exposed to outside.
    Type: Application
    Filed: March 21, 2018
    Publication date: September 26, 2019
    Inventor: Hae Chan PARK
  • Patent number: 10373971
    Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: August 6, 2019
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Jang Won Kim, Gong Hyun Sa
  • Patent number: 10296480
    Abstract: A data processing system includes a central processing unit (CPU), a control block configured to interface with the CPU, a cache memory configured to interface with the control block and arranged to be spaced from the CPU by a first distance, and a combined memory block configured to interface with the control block, arranged to be spaced from the CPU by a second distance larger than the first distance, and configured of a working memory and a storage memory. The combined memory block is configured of a plurality of stacked memory layers, each configured of a plurality of variable resistance memory cells. The working memory is allocated to one memory layer selected among the plurality of memory layers. The storage memory is allocated to remaining memory layers among the plurality of memory layers.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: May 21, 2019
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Sung Cheoul Kim, Tae Ho Kim
  • Publication number: 20190115425
    Abstract: A semiconductor device includes a stack structure located on a substrate and includes a first region, in which sacrificial layers and insulating layers are alternately stacked, and a second region, in which conductive layers and insulating layers are alternately stacked. The stack structure also includes a first slit insulating layer located at a boundary between the first region and the second region, wherein the first slit insulating layer penetrates the stack structure and extends in one direction. The stack structure further includes a plurality of slit insulating patterns located in the second region, wherein the plurality of slit insulating patterns penetrate the stack structure and are arranged along the one direction. At least one conductive layer among the conductive layers is bent between the first slit insulating layer and the slit insulating patterns.
    Type: Application
    Filed: December 5, 2018
    Publication date: April 18, 2019
    Applicant: SK hynix Inc.
    Inventors: Hae Chan PARK, Jae Taek KIM
  • Patent number: 10177224
    Abstract: A semiconductor device includes a stack structure located on a substrate and includes a first region, in which sacrificial layers and insulating layers are alternately stacked, and a second region, in which conductive layers and insulating layers are alternately stacked. The stack structure also includes a first slit insulating layer located at a boundary between the first region and the second region, wherein the first slit insulating layer penetrates the stack structure and extends in one direction. The stack structure further includes a plurality of slit insulating patterns located in the second region, wherein the plurality of slit insulating patterns penetrate the stack structure and are arranged along the one direction. At least one conductive layer among the conductive layers is bent between the first slit insulating layer and the slit insulating patterns.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: January 8, 2019
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Jae Taek Kim
  • Publication number: 20180053779
    Abstract: A manufacturing method of a semiconductor device may be provided. The method may include forming stacks including interlayer insulating layers and separated by a slit, the interlayer insulating layers surrounding a channel layer and stacked to be spaced apart from one another with an interlayer space interposed therebetween. The method may include forming a conductive pattern filling the interlayer space. The method may include forming an isolation layer on a surface of the conductive pattern by oxidizing a portion of the conductive pattern by performing an oxidizing process.
    Type: Application
    Filed: April 14, 2017
    Publication date: February 22, 2018
    Applicant: SK hynix Inc.
    Inventors: Hae Chan PARK, Jang Won KIM, Gong Hyun SA
  • Patent number: 9818481
    Abstract: A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell includes a data storage material and a non-silicon-substrate-based type bidirectional access device coupled in series, a path setting circuit coupled between the bit line and the word line, suitable for providing a program pulse toward the bit line or the word line based on a path control signal, a forward write command, and a reverse write command, and a control unit suitable for providing a write path control signal, a forward program command, and a reverse program command based on an external command signal.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: November 14, 2017
    Assignee: SK Hynix Inc.
    Inventors: Hae Chan Park, Myoung Sub Kim, Se Ho Lee, Seung Yun Lee
  • Publication number: 20170162262
    Abstract: A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell includes a data storage material and a non-silicon-substrate-based type bidirectional access device coupled in series, a path setting circuit coupled between the bit line and the word line, suitable for providing a program pulse toward the bit line or the word line based on a path control signal, a forward write command, and a reverse write command, and a control unit suitable for providing a write path control signal, a forward program command, and a reverse program command based on an external command signal.
    Type: Application
    Filed: February 16, 2017
    Publication date: June 8, 2017
    Inventors: Hae Chan PARK, Myoung Sub KIM, Se Ho LEE, Seung Yun LEE
  • Publication number: 20170148985
    Abstract: A semiconductor apparatus includes a variable resistor including a variable resistance layer, which is formed to surround on an inner surface of a resistive region, and an insert layer which is formed in the variable resistance layer and has a resistivity being different from that of the variable resistance layer.
    Type: Application
    Filed: February 2, 2017
    Publication date: May 25, 2017
    Inventor: Hae Chan PARK
  • Patent number: 9613690
    Abstract: A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell includes a data storage material and a non-silicon-substrate-based type bidirectional access device coupled in series, a path setting circuit coupled between the bit line and the word line, suitable for providing a program pulse toward the bit line or the word line based on a path control signal, a forward write command, and a reverse write command, and a control unit suitable for providing a write path control signal, a forward program command, and a reverse program command based on an external command signal.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: April 4, 2017
    Assignee: SK Hynix Inc.
    Inventors: Hae Chan Park, Myoung Sub Kim, Se Ho Lee, Seung Yun Lee