Patents by Inventor Hai-Ching Chen

Hai-Ching Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10408998
    Abstract: A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: September 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hao Tseng, Wan-Yu Lee, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20190219762
    Abstract: A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer.
    Type: Application
    Filed: March 22, 2019
    Publication date: July 18, 2019
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo, Hai-Ching Chen, Tien-I Bao
  • Patent number: 10353147
    Abstract: A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45° angle with a major surface of the substrate. The etchant comprises a base, a surfactant, and an oxidant. The oxidant may be hydrogen peroxide.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yu Lee, Ying-Hao Kuo, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20190146165
    Abstract: A method of making an optical bench includes forming a trench in a substrate and wherein the trench has a sloping side, forming a reflector layer over the sloping side, depositing a redistribution layer over the substrate, disposing an under bump metallization (UBM) layer over the redistribution layer, depositing a passivation layer over the redistribution layer and surrounding sidewalls of the UBM layer, and mounting an optical component over an uppermost portion of the substrate, wherein the optical component is electrically connected to a through substrate via (TSV) extending through the substrate. The reflector layer is configured to reflect an electromagnetic wave from the optical component, and wherein the optical component is mounted outside the trench.
    Type: Application
    Filed: January 14, 2019
    Publication date: May 16, 2019
    Inventors: Wan-Yu LEE, Chun-Hao TSENG, Hai-Ching CHEN, Tien-I BAO
  • Publication number: 20190131240
    Abstract: A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.
    Type: Application
    Filed: December 26, 2018
    Publication date: May 2, 2019
    Inventors: Chi-Lin Teng, Jung-Hsun Tsai, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen, Tien-I Bao
  • Patent number: 10261248
    Abstract: A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui Hsieh Lai, Ying-Hao Kuo, Hai-Ching Chen, Tien-I Bao
  • Patent number: 10211097
    Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: February 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yen Huang, Kai-Fang Cheng, Chi-Lin Teng, Shao-Kuan Lee, Hai-Ching Chen
  • Publication number: 20190025514
    Abstract: An apparatus comprises a substrate having a plateau region and a trench region, a metal layer over the plateau region, a semiconductor component over the trench region, wherein a gap is between the plateau region and the semiconductor component, an adhesion promoter layer over the plateau region, the semiconductor component and the gap, a dielectric layer over the adhesion promoter layer and a bonding interface formed between the adhesion promoter layer and the dielectric layer, wherein the bonding interface comprises a chemical structure comprising a first dielectric material of the adhesion promoter layer and a second dielectric material of the dielectric layer.
    Type: Application
    Filed: September 25, 2018
    Publication date: January 24, 2019
    Inventors: Chun-Hao Tseng, Ying-Hao Kuo, Kai-Fang Cheng, Hai-Ching Chen, Tien-I Bao
  • Patent number: 10180547
    Abstract: An optical bench on substrate includes a substrate and a trench formed inside the substrate and having a sloping side. A reflector layer is formed over the sloping side. An optical component is mounted over the substrate. The reflector layer is configured to reflect an electromagnetic wave to or from the optical component.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: January 15, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wan-Yu Lee, Chun-Hao Tseng, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20180374708
    Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
    Type: Application
    Filed: August 31, 2018
    Publication date: December 27, 2018
    Inventors: Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao
  • Patent number: 10163797
    Abstract: A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Lin Teng, Jung-Hsun Tsai, Kai-Fang Cheng, Hsin-Yen Huang, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20180350669
    Abstract: A semiconductor device includes a first metal wiring layer, an interlayer insulating layer formed over the first metal layer, a second metal wiring structure embedded in the interlayer dielectric layer and connected to the first metal wiring layer, and an etch-stop layer disposed between the first metal wiring and the first interlayer dielectric layer. The etch-stop layer includes one or more sub-layers. The etch-stop layer includes a first sub-layer made of an aluminum-based insulating material, hafnium oxide, zirconium oxide or titanium oxide.
    Type: Application
    Filed: July 30, 2018
    Publication date: December 6, 2018
    Inventors: Hsin-Yen HUANG, Kai-Fang CHENG, Chi-Lin TENG, Shao-Kuan LEE, Hai-Ching CHEN
  • Patent number: 10121698
    Abstract: Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: November 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hsiang-Huan Lee, Shau-Lin Shue, Kuang-Kuo Koai, Hai-Ching Chen, Tung-Ching Tseng, Wen-Cheng Yang, Chung-En Kao, Ming-Han Lee, Hsin-Yen Huang
  • Publication number: 20180308689
    Abstract: The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Inventors: Bo-Jiun Lin, Hai-Ching Chen, Tien-I Bao
  • Patent number: 10090245
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate and the first conductive structure. The semiconductor device structure includes a second conductive structure over the first conductive structure and extending into the first dielectric layer. The second conductive structure is electrically connected to the first conductive structure. The semiconductor device structure includes a cover layer between the second conductive structure and the first dielectric layer. The cover layer surrounds the second conductive structure, the second conductive structure passes through the cover layer and is partially between the cover layer and the first conductive structure, and the cover layer includes a metal oxide.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kai-Fang Cheng, Chi-Lin Teng, Hai-Ching Chen, Hsin-Yen Huang, Tien-I Bao, Jung-Hsun Tsai
  • Patent number: 10082626
    Abstract: A method comprises forming a plateau region and a trench region over a substrate, wherein the trench region comprises a slope and a flat bottom, depositing a reflecting layer over the flat bottom and a portion of the slope, depositing a first adhesion promoter layer over the reflecting layer, applying a first curing process to the first adhesion promoter layer, wherein, after the first curing process finishes, the reflecting layer and the first adhesion promoter layer form a first bonding interface, depositing a bottom cladding layer deposited over the first adhesion promoter layer, applying a second curing process to the bottom cladding layer to form a second bonding interface layer, depositing a core layer over the bottom cladding layer and depositing a top cladding layer over the core layer.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hao Tseng, Ying-Hao Kuo, Kai-Fang Cheng, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20180254212
    Abstract: A method for forming an interconnect structure includes forming an insulating layer on a substrate. A damascene opening is formed through a thickness portion of the insulating layer. A diffusion barrier layer is formed to line the damascene opening. A conductive layer is formed overlying the diffusion barrier layer to fill the damascene opening. A carbon-containing metal oxide layer is formed on the conductive layer and the insulating layer.
    Type: Application
    Filed: May 3, 2018
    Publication date: September 6, 2018
    Inventors: Bo-Jiun Lin, Hai-Ching Chen, Tien-I Bao
  • Patent number: 10068770
    Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: September 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao
  • Publication number: 20180226293
    Abstract: A device includes a substrate; a first layer over the substrate, the first layer containing a metallic material, wherein the first layer includes a trench; and a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.
    Type: Application
    Filed: April 2, 2018
    Publication date: August 9, 2018
    Inventors: Bo-Jiun Lin, Ching-Yu Chang, Hai-Ching Chen, Tien-I Bao
  • Publication number: 20180211911
    Abstract: A first layer is located over a substrate. The first layer includes a first dielectric component and a first conductive component. A first etching stop layer is located over the first dielectric component. A metal capping layer is located over the first conductive component. A second etching stop layer is located over the first etching stop layer and over the metal capping layer. A second layer is located over the second etching stop layer. The second layer includes a second dielectric component and a second conductive component. A third conductive component electrically interconnects the second conductive component to the first conductive component.
    Type: Application
    Filed: March 19, 2018
    Publication date: July 26, 2018
    Inventors: Yung-Hsu Wu, Hai-Ching Chen, Jung-Hsun Tsai, Shau-Lin Shue, Tien-I Bao