Abstract: A word line driver circuit for use in a memory array including multiple memory cells and multiple word lines coupled to the memory cells for selectively accessing the memory cells includes a driver adapted to generate a word line signal as a function of a first set of address signals received by the word line driver circuit. The circuit further includes a switching circuit having a plurality of output nodes, the output nodes connected to respective ones of the plurality of word lines, and having an input node connected to an output of the driver and adapted to receive the word line signal. The switching circuit is operative to direct the word line signal to a selected one of the word lines during a memory access as a function of at least one control signal. Between a given pair of memory accesses, the output nodes and the input node of the switching circuit are held to a same prescribed voltage level to thereby substantially eliminate a leakage current path in the switching circuit.

Abstract: A sense amplifier includes a first sensing element and a second sensing element redundant to the first sensing element. The sense amplifier further comprises a switch circuit configured to switch between the first and second sensing elements when an offset of the sense amplifier is greater than a prescribed amount.

Abstract: A memory circuit having reduced power consumption includes a plurality of memory sub-arrays and a shared circuit coupled to each of the memory sub-arrays. Each memory sub-array includes at least one row circuit, at least one column circuit, and a plurality of memory cells operatively coupled to the row and column circuits. The row and column circuits are operative to provide selective access to one or more of the memory cells. The shared circuit includes circuitry, external to the memory sub-arrays, which is operative to control one or more functions of the memory sub-arrays as a function of at least one control signal supplied to the memory circuit. The memory circuit is operative, with at least one of the memory sub-arrays operative, with one or more of the memory sub-arrays powered and concurrently with one or more of the memory sub-arrays unpowered.

Abstract: A row line driver circuit for use in a memory array including multiple memory cells and multiple row lines coupled to the memory cells for selectively accessing the memory cells includes an output stage adapted for connection to a corresponding one of the row lines and a control circuit connected to the output stage. The output stage is operative during an active phase of a given memory cycle to drive the corresponding row line to a potential as a function of at least one address signal received by the driver circuit. The control circuit is operative to generate at least one control signal for disabling the output stage at least during an inactive phase of the memory cycle to thereby substantially eliminate a leakage current path in the driver circuit.

Abstract: A memory cell for use in a content-addressable memory comprises a first latch and a second latch. The first latch is operative to store a first bit associated with a first stored word, while the second latch is operative to store a second bit associated with a second stored word. The first and second latches collectively comprise a plurality of latch transistors. Each of the latch transistors comprises a respective channel. The channels of the latch transistors are oriented in substantially the same direction, resulting in a very compact memory cell implementation.

Abstract: A row line driver circuit for use in a memory array including multiple memory cells and multiple row lines coupled to the memory cells for selectively accessing the memory cells includes an output stage adapted for connection to a corresponding one of the row lines and a control circuit connected to the output stage. The output stage is operative during an active phase of a given memory cycle to drive the corresponding row line to a potential as a function of at least one address signal received by the driver circuit. The control circuit is operative to generate at least one control signal for disabling the output stage at least during an inactive phase of the memory cycle to thereby substantially eliminate a leakage current path in the driver circuit.

Abstract: A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by reducing the duration of the precharge cycle during each read cycle so that the associated leakage current will flow for a shorter time period during each cycle. The precharge phase is positioned at the beginning of each read cycle, prior to the evaluation phase. The precharge phase is terminated by a subsequent clock edge or by an internal time out prior to a subsequent clock edge. The time interval between when the columns reach their precharge voltage and the evaluation phase begins is reduced.

Abstract: A memory cell for use in a content-addressable memory comprises a first latch and a second latch. The first latch is operative to store a first bit associated with a first stored word, while the second latch is operative to store a second bit associated with a second stored word. The first and second latches collectively comprise a plurality of latch transistors. Each of the latch transistors comprises a respective channel. The channels of the latch transistors are oriented in substantially the same direction, resulting in a very compact memory cell implementation.

Abstract: A memory device comprises a memory array and error correction circuitry coupled to the memory array. The error correction circuitry is configured to identify, in a data word retrieved from the memory array, at least one bit position corresponding to a predetermined defect location in the memory array, and to generate a corrected data word by automatically inverting a logic value at the identified bit position. This automatic logic inversion approach is particularly well suited for use in correcting output data errors associated with via defects and weak bit defects in high-density ROM devices.

Abstract: A single-ended sensing circuit is provided for use with a memory circuit including a plurality of bit lines and a plurality of memory cells connected to the bit lines. The sensing circuit includes at least one charge sharing circuit and at least one switching circuit connected to the charge sharing circuit. The switching circuit is operative to selectively connect the charge sharing circuit to at least a given one of the bit lines as a function of a first control signal supplied to the switching circuit. The sensing circuit further includes at least one comparator circuit connected to the given bit line. The comparator circuit is operative to generate an output signal indicative of a logical state of a memory cell connected to the given bit line. The charge sharing circuit is operative to remove an amount of charge on the given bit line so as to reduce a voltage on the given bit line in conjunction with a read access of the memory cell.

Abstract: A sensing circuit for use with a CAM circuit including multiple match lines and multiple CAM cells connected to the match lines includes at least one charge sharing circuit and at least one switching circuit connected to the charge sharing circuit. The switching circuit is operative to selectively connect the charge sharing circuit to a corresponding one of the match lines as a function of a first control signal supplied to the switching circuit. The sensing circuit further includes at least one comparator circuit connected to the corresponding match line and operative to generate an output signal indicative of a match between search data supplied to at least a given one of the CAM cells connected to the corresponding match line and data stored in the given CAM cell. The charge sharing circuit is operative to remove an amount of charge on the corresponding match line so as to reduce a voltage on the corresponding match line in conjunction with a search operation of the CAM cell.

Abstract: Certain embodiments of the inventions provide an integrated circuit (IC) having a processor operatively coupled to a PVT (process-voltage-temperature) source and an adjustable memory. The processor receives from the source an input characterizing the present PVT condition and generates a command for the memory based on that input. In response to the command, the memory adjusts its internal circuit structure, clock speed, and/or operating voltage(s) to optimize its performance for the present PVT condition. Advantageously, the ability to adjust the memory so that it can maintain its functionality and deliver an acceptable level of performance under unfavorable PVT conditions provides additional flexibility in choosing circuit design options, which can produce area savings and/or increase the yield of acceptable ICs during manufacture.

Abstract: A sensing circuit for use with a CAM circuit including multiple match lines and multiple CAM cells connected to the match lines includes at least one charge sharing circuit and at least one switching circuit connected to the charge sharing circuit. The switching circuit is operative to selectively connect the charge sharing circuit to a corresponding one of the match lines as a function of a first control signal supplied to the switching circuit. The sensing circuit further includes at least one comparator circuit connected to the corresponding match line and operative to generate an output signal indicative of a match between search data supplied to at least a given one of the CAM cells connected to the corresponding match line and data stored in the given CAM cell. The charge sharing circuit is operative to remove an amount of charge on the corresponding match line so as to reduce a voltage on the corresponding match line in conjunction with a search operation of the CAM cell.

Abstract: A single-ended sensing circuit is provided for use with a memory circuit including a plurality of bit lines and a plurality of memory cells connected to the bit lines. The sensing circuit includes at least one charge sharing circuit and at least one switching circuit connected to the charge sharing circuit. The switching circuit is operative to selectively connect the charge sharing circuit to at least a given one of the bit lines as a function of a first control signal supplied to the switching circuit. The sensing circuit further includes at least one comparator circuit connected to the given bit line. The comparator circuit is operative to generate an output signal indicative of a logical state of a memory cell connected to the given bit line. The charge sharing circuit is operative to remove an amount of charge on the given bit line so as to reduce a voltage on the given bit line in conjunction with a read access of the memory cell.

Abstract: A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by reducing the duration of the precharge cycle during each read cycle so that the associated leakage current will flow for a shorter time period during each cycle. The precharge phase is positioned at the beginning of each read cycle, prior to the evaluation phase. The precharge phase is terminated by a subsequent clock edge or by an internal time out prior to a subsequent clock edge. The time interval between when the columns reach their precharge voltage and the evaluation phase begins is reduced.

Abstract: A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by applying a biased gate voltage (relative to a source voltage) to the gate of at least one of transistor in the array. The biased gate voltage is applied at least during a precharge phase of a read cycle. When the array transistors are n-channel transistors, the biased voltage is a negative bias voltage (relative to the source voltage). When the array transistors are p-channel transistors, the biased voltage is a positive bias voltage (relative to the source voltage). Applying a negative backgate bias to the transistor's p-well contact can also reduce n-channel transistor subthreshold leakage current. Thus, for an n-channel array, a negative gate voltage and backgate bias (optional) are applied to cell transistors in the off state.

Abstract: A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by precharging only a portion of the columns in a read only memory array during a given read cycle. The portion of the columns that are precharged is limited to a subset of columns that includes those columns that will be read during a given read cycle. A read column address is decoded to precharge only the portion of the columns of transistors that will be read during the given read cycle. The columns of transistors can be grouped into a plurality of sub-arrays and only those sub-arrays having columns that will be read during a given read cycle are precharged during the read cycle.

Abstract: A method and apparatus are provided for reducing leakage current in a read only memory device. Leakage current is reduced by precharging only a portion of the columns in a read only memory array during a given read cycle. The portion of the columns that are precharged is limited to a subset of columns that includes those columns that will be read during a given read cycle. A read column address is decoded to precharge only the portion of the columns of transistors that will be read during the given read cycle. The columns of transistors can be grouped into a plurality of sub-arrays and only those sub-arrays having columns that will be read during a given read cycle are precharged during the read cycle.

Abstract: The present invention provides a read-only memory (ROM) architecture. An exemplary ROM array includes a plurality of columns, a plurality of rows, a first plurality of transistors or other switches representing a “0” data state or low voltage state, and a second plurality of transistors or other switches representing a “1” data state or high voltage state. Each transistor has a corresponding drain coupled to a column and a gate coupled to a row. Each transistor of the first plurality has a source coupled to a source voltage bus, and each transistor of the second plurality has a source not coupled to the source voltage bus, through use of a programmable contact window during fabrication. In various embodiments, for a selected column, drains of pair-wise adjacent transistors share a common drain-column contact and common diffusion region.

Abstract: The present invention provides a read-only memory (ROM) architecture. An exemplary ROM array includes a plurality of columns, a plurality of rows, a first plurality of transistors or other switches representing a “0” data state or low voltage state, and a second plurality of transistors or other switches representing a “1” data state or high voltage state. Each transistor has a corresponding drain coupled to a column and a gate coupled to a row. Each transistor of the first plurality has a source coupled to a source voltage bus, and each transistor of the second plurality has a source not coupled to the source voltage bus, through use of a programmable contact window during fabrication. In various embodiments, for a selected column, drains of pair-wise adjacent transistors share a common drain-column contact and common diffusion region.