Abstract: A reconfiguration memory device is provided associated with a main memory array. The reconfiguration memory device generates a spare address in real time corresponding to a faulty address. The reconfiguration memory device is coupled to an address line, so that when address information is received for the main memory array, the address information is also received by the reconfiguration memory device. The reconfiguration memory device is adapted to send an output signal that results in the address in the spare memory address array being addressed, if the received address information corresponds to a stored faulty address. The output signal includes a spare control signal that directs components to look to the output of the spare memory.

Abstract: A reconfiguration memory device is provided associated with a main memory array. The reconfiguration memory device generates a spare address in real time corresponding to a faulty address. The reconfiguration memory device is coupled to an address line, so that when address information is received for the main memory array, the address information is also received by the reconfiguration memory device. The reconfiguration memory device is adapted to send an output signal that results in the address in the spare memory address array being addressed, if the received address information corresponds to a stored faulty address. The output signal includes a spare control signal that directs components to look to the output of the spare memory.

Abstract: A computer main memory is divided into multiple physically-separated arrays of memory cells. Each array has associated with it an array of spare memory cells. The array of spare memory cells is located adjacent to its associated main memory cell array. The rows in the spare memory cell array are aligned with the rows in the associated main memory cell array. The main memory blocks are divided into subblocks. Within each subblock, all columns are addressed by a single multiplexer unique to that subblock. A data input bus and a data output bus is provided corresponding to each subblock in the main memory block. Each data input bus and data output bus is electrically coupled to a main memory bus, and each spare memory block. Data can therefore be readily directed either to one of the subblocks in the main memory or to one of the spare memory blocks.

Abstract: A computer main memory is divided into multiple physically-separated arrays of memory cells. Each array has associated with it an array of spare memory cells. The array of spare memory cells is located adjacent to its associated main memory cell array. The rows in the spare memory cell array are aligned with the rows in the associated main memory cell array. The main memory blocks are divided into subblocks. Within each subblock, all columns are addressed by a single multiplexer unique to that subblock. A data input bus and a data output bus is provided corresponding to each subblock in the main memory block. Each data input bus and data output bus is electrically coupled to a main memory bus, and each spare memory block. Data can therefore be readily directed either to one of the subblocks in the main memory or to one of the spare memory blocks.