Abstract: A memory device is provided. The memory device includes an array of memory cells arranged, a plurality of word lines, and a peripheral circuit configured to perform multi-pass programming on a selected row of memory cells coupled to a selected word line. The multi-pass programming includes a plurality of programming passes. Each of the programming passes includes a programming operation and a verify operation. To perform the multi-pass programming, the peripheral circuit is configured to, in a non-last programming pass of memory cells, perform a negative gate stress (NGS) operation on a memory cell in the selected row of memory cells between the programming operation and the verify operation; and at a same time, perform a NGS operation on a memory cell in an unselected row of memory cells coupled to an unselected word line of the word lines. The unselected word line is adjacent to the selected word line.

Abstract: A method, computer program product, and computing system for: receiving an initial portion of an encounter record; processing the initial portion of the encounter record to generate initial content for a medical report; receiving one or more additional portions of the encounter record; and processing the one or more additional portions of the encounter record to modify the medical report.

Abstract: A system for millimeter wave-based fire detecting and rescuing and a method thereof are provided, the system including: an environmental obtaining device, a millimeter wave detector, a wireless transmitter, and a monitoring terminal, which are interconnected and arranged in an environment. The environmental obtaining device is configured to collect environmental information and send the environmental information to the wireless transmitter when the environmental information is determined to include fire information. The millimeter wave detector is configured to perform all-weather scanning on the environment to obtain characteristics and location information of a living organism in the environment, and send the characteristics and location information to the wireless transmitter. The wireless transmitter is configured to report the above information to the monitoring terminal through a millimeter wave, and the monitoring terminal stores the characteristics and location information.

Abstract: A filtering method and apparatus are provided, and the method includes: performing spectrum shifting on a first signal to obtain a second signal, where the first signal includes a first valid signal band and a first to-be-suppressed signal band, a demarcation point of the first valid signal band and the first to-be-suppressed signal band in the first signal is a first boundary point, the first boundary point corresponds to a second boundary point in the second signal, a frequency of the second boundary point is equal to a frequency of a first side frequency point of the filter, and a frequency range corresponding to the first valid signal band in the second signal falls within a frequency range corresponding to a passband of the filter (S301); and filtering the second signal by using the filter, to obtain the first valid signal band (S302).

Abstract: A compound of formula (I) or an optical isomer thereof, and pharmaceutically acceptable salts, prodrugs, aquo-complexes or non-aqueous-solvent complexes thereof are provided. Experiments prove that, compared with a control compound MGL-3196, the compound of formula (I), which is obtained through specific substitution sites and specific substitution types, is higher in agonist activity to THR-beta and significantly improved in selectivity on THR-beta/THR-alpha. The compound can be used in preparing THR-beta agonist and drugs for treating adaption diseases (including dyslipidemia, hypercholesteremia, non-alcoholic steatohepatitis and non-alcoholic fatty liver disease) applicable to the THR-beta agonist.

Abstract: A memory system includes a plurality of blocks of memory blocks, each including a plurality of memory cells. The method for programming the memory system includes during a program process, performing a first program operation to program a first memory block, waiting for a delay time after the first program operation is completed, after waiting for the delay time, performing an all-level threshold voltage test to determine if threshold voltages of the first memory block are greater than corresponding threshold voltages, and performing a second program operation to program the first memory block according to a result of the all-level threshold voltage test.

Abstract: In a method for reading a memory device including a first memory cell string, in a pre-verify stage, a first verify voltage is applied on a gate terminal of a selected memory cell of the first memory cell string, where the selected memory cell is programmed and arranged between a first adjacent memory cell and a second adjacent memory cell. A first bias voltage is applied on a gate terminal of at least one memory cell of the first memory cell string that is not programmed. In a verify stage, a second verify voltage is applied on the gate terminal of the selected memory cell of the first memory cell string. A second bias voltage is applied on the gate terminal of the at least one memory cell of the first memory cell string that is not programmed, where the second bias voltage is smaller than the first bias voltage.

Abstract: A memory device is provided. The memory device includes an array of memory cells arranged in a plurality of rows, a plurality of word lines respectively coupled to the plurality of rows of the memory cells, and a peripheral circuit coupled to the word lines. The peripheral circuit is configured to convert a first value to a second value based on a mapping relationship between a read gray code and a program gray code, perform a program operation to program the second value into a memory cell as a state based on the read gray code, and perform a read operation to read out the state from the memory cell based on the read gray code to be the first value.

Abstract: A method for programming a three-dimensional (3D) memory device is provided. The 3D memory device has a plurality of memory strings with memory cells vertically stacked, and each memory cell is addressable through a word line and a bit line. The method for programming the 3D memory device includes the following steps: applying a program voltage on a selected word line; applying a first pass voltage on a first group of unselected word lines; and applying a second pass voltage on a second group of unselected word lines, wherein the second pass voltage is different from the first pass voltage.

Abstract: In certain aspects, a memory device includes a memory cell array having rows of memory cells, word lines respectively coupled to the rows of memory cells, and a peripheral circuit coupled to the memory cell array through the word lines. Each memory cell is configured to store a piece of N-bits data in one of 2N levels, where N is an integer greater than 1. The level corresponds to one of 2N pieces of N-bits data. The peripheral circuit is configured to program, in a first pass, a row of target memory cells, such that each of the row of target memory cells is programmed into one of 2N/m intermediate levels based on the piece of N-bits data to be stored in the target memory cell, where m is an integer greater than 1. The peripheral circuit is also configured to program, in a second pass after the first pass, the row of target memory cells, such that each target memory cell is programmed into one of the 2N levels based on the piece of N-bits data to be stored in the target memory cell.

Abstract: A memory device is provided. The memory device includes an array of memory cells arranged, a plurality of word lines, and a peripheral circuit configured to perform multi-pass programming on a selected row of memory cells coupled to a selected word line. The multi-pass programming includes a plurality of programming passes. Each of the programming passes includes a programming operation and a verify operation. To perform the multi-pass programming, the peripheral circuit is configured to, in a non-last programming pass of memory cells, perform a negative gate stress (NGS) operation on a memory cell in the selected row of memory cells between the programming operation and the verify operation; and at a same time, perform a NGS operation on a memory cell in an unselected row of memory cells coupled to an unselected word line of the word lines. The unselected word line is adjacent to the selected word line.

Abstract: A memory device is provided. The memory device includes an array of memory cells arranged in a plurality of rows, a plurality of word lines respectively coupled to the plurality of rows of the memory cells; and a peripheral circuit coupled to the word lines and configured to perform multi-pass programming on a selected row of memory cells coupled to a selected word line of the word lines. The multi-pass programming includes a plurality of programming passes, each of the programming passes having a programming operation and a verify operation. To perform the multi-pass programming, the peripheral circuit is configured to, in a non-last programming pass, perform a negative gate stress (NGS) operation on each memory cell in the selected row of memory cells between the programming operation and the verify operation.

Abstract: Technical solutions are described for controlling operation of an electric machine such as a permanent magnet synchronous motor (PMSM) drive or motor control system to limit battery current and protect a battery from excessive discharging or charging current from the PMSM drive. Systems and methods employ a torque control algorithm for PMSMs that uses a battery current limit constraint when generating current commands during each of a maximum torque per ampere (MTPA) operation, and maximum torque per voltage (MTPV) operation. Torque search operations are performed in each of the MTPA and MTPV operation regions in a PMSM drive system until current commands are achieved under a given battery current limit constraint and while maintaining maximum voltage utilization throughout all PMSM operation regions.

Abstract: An aromatic amine androgen receptor (AR) and BET targeting protein degradation chimera compound is represented by formula I. Experimental results show that the compound can target and degrade both AR and BRD4, and down-regulate the expression of AR and BRD4 proteins; the compound can inhibit the proliferation of a variety of prostate cancer cells; the compound can inhibit the proliferation of a prostate cancer cell line LNCaP/AR, which overexpresses the AR, and can achieve a good inhibition effect on a prostate cancer cell line 22RV1, which is resistant to a marketed prostate cancer drug (enzalutamide). The compound also shows good metabolic stability, and has a good application prospect in the preparation of an AR and/or BET protein degradation targeting chimera, and a drug for the treatment of related diseases regulated by the AR and BET.

Abstract: The present invention features compositions and methods for preventing or treating neuroinflammation, amyloidopathy or tauopathy by inhibiting Acyl-CoA:Cholesterol Acyltransferase activity, in particular with brain-permeable inhibitors encapsulated in a stealth liposome-based nanoparticle. Stealth liposome-based nanoparticles for reducing or attenuating amyloidopathy or tauopathy are also provided.

Abstract: A memory system includes a plurality of memory cells, and the memory cells are multiple-level cells. The memory system performs program operations to program the memory cells. After each program operation, at least one threshold voltage test is performed to determine if threshold voltages of the memory cells are greater than the verification voltage. When the threshold voltage of a first memory cell is determined to be greater than a first verification voltage, the first memory cell will be inhibited from being programmed during the next program operation. When the threshold voltage of a second memory cell is determined to newly become greater than a second verification voltage, where the second verification voltage is greater than the first verification voltage, the second memory cell will be programmed again during the next program operation.

Abstract: In a method for reading a memory device including a first memory cell string, in a pre-verify stage, a first verify voltage is applied on a gate terminal of a selected memory cell of the first memory cell string, where the selected memory cell is programmed and arranged between a first adjacent memory cell and a second adjacent memory cell. A first bias voltage is applied on a gate terminal of at least one memory cell of the first memory cell string that is not programmed. In a verify stage, a second verify voltage is applied on the gate terminal of the selected memory cell of the first memory cell string. A second bias voltage is applied on the gate terminal of the at least one memory cell of the first memory cell string that is not programmed, where the second bias voltage is smaller than the first bias voltage.

Abstract: The present disclosure relates to a method and a device for recognizing hand gestures in real-time. A shape is given as an input in a form of a binary image. The shape contour is partitioned into radial and angular spaces by an Angular Radial Bin distribution including multiple concentric circles and angular space partitions in a way that multiple angular radial sections are created denoted Angular Radial Bins. The ARB distribution is angle tilted through its centre of mass multiple times and the same procedure is repeated in order to capture a shape descriptor from different angle perspectives. A shape descriptor is calculated for each of an angle tilted instance of the ARB distribution belonging to a sequence of angle tilted instances of the ARB distribution.

Abstract: The compound shown in formula I has dual inhibitory effects on AR and BRD4. The compound is not only capable of inhibiting the proliferation of androgen receptor AR multi-expressed prostate cancer cell line LNCAP/AR, but also shows good inhibitory effects on prostate cancer lines VCaP and RRRV1, which are resistant to prostate cancer drugs (enzalutamide) on the market. The compound is also capable of being used for preparing proteolysis-targeting chimeras (PROTACs) for inducing the degradation of AR/BRD4 dual targets, and has good prospects for application in the preparation of drugs for the treatment of AR and BRD4-related diseases.

Abstract: The extraction system contains secondary amides and alkyl alcohols which are separately used as the extractants for extracting lithium and boron and consist of a single compound or a mixture of two or more compounds, and the total number of carbon atoms in their molecules are 12˜18 and 8˜20 respectively; the extraction system has a freezing point less than 0° C. With a volume ratio of an organic phase and a brine phase being 1˜10:1, at a brine density of 1.25˜1.38 g/cm3, at a brine pH value of 0˜7 and at a temperature of 0˜50° C., a single-stage or multi-stage countercurrent extraction and a stripping are conducted to obtain a water phase with a low magnesium-lithium ratio, which is subjected to concentration, impurity removal and preparation to get lithium chloride, lithium carbonate, lithium hydroxide and boric acid respectively. Water is used for stripping, greatly reducing the consumption of acid and base.