Patents by Inventor Hailing Wang

Hailing Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11926969
    Abstract: Fibrous structures containing filaments and solid additives, and more particularly to fibrous structures containing filaments and solid additives wherein the fibrous structure has three or more regions that exhibit different characteristics and/or properties and methods for making same, are provided.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: March 12, 2024
    Assignee: The Procter & Gamble Company
    Inventors: Fei Wang, Arman Ashraf, Michael Donald Suer, John Daniel Algers, Cunming Song, Hailing Bao, Antonius Lambertus De Beer, David John Pung, Steven Lee Barnholtz, Paul Thomas Weisman, Alexander P. King
  • Publication number: 20240079314
    Abstract: A circuit can include a capacitor that has a semiconductor layer, a dielectric layer, and a conductive layer. The circuit can include an insulating layer and a metal or conductive layer. The metal layer can have a first portion that has a first plurality of fingers, and a second portion that has a second plurality of fingers, which can be interdigitated with the first plurality of fingers. The circuit can include one or more first electrical connections that electrically couple the first portion of the metal layer to the semiconductor layer of the capacitor. The circuit can include one or more second electrical connections that electrically couple the second portion of the metal layer to the conductive layer of the capacitor. A capacitance provided by the interdigitated first and second pluralities of fingers can be at least about 3% of a capacitance provided by the capacitor.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 7, 2024
    Inventors: Hailing Wang, Guillaume Alexandre Blin, David Scott Whitefield, Michael Joseph McPartlin, Lui Ray Lam
  • Publication number: 20240061384
    Abstract: The present invention discloses a resilience-enhanced simulation method for container logistics supply chain based on adaptive fuzzy double feedback, specific steps comprising: applying a container logistics supply chain system to simulate the impact of adverse events; Designing a two-dimensional resilience index to measure the overall resilience of the container logistics supply chain system; Based on this simulation system, an adaptive fuzzy dual feedback control structure is established and a resilience enhanced method is proposed, so that the output of unfinished container operations affected by adverse events converge to zero quickly. By simulating the supply chain system under step demand, the effectiveness of the resilience enhanced control method of container logistics supply chain is verified.
    Type: Application
    Filed: August 22, 2023
    Publication date: February 22, 2024
    Inventors: Bowei Xu, Weiting Liu, Junjun Li, Hailing Wang, Tianmiao Gao, Qiuju Xiong, Wei Chen
  • Publication number: 20240030908
    Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.
    Type: Application
    Filed: June 13, 2023
    Publication date: January 25, 2024
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, Jerod F. Mason, David Scott Whitefield, Paul T. DiCarlo
  • Patent number: 11842947
    Abstract: The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly. The source fingers and the drain fingers can be arranged in alternating rows.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: December 12, 2023
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, David Scott Whitefield, Paul T. DiCarlo
  • Patent number: 11742408
    Abstract: A method of fabricating a cascode amplifier including a common-source device and a common-gate device includes performing one or more of ion implantation of a well of the common-source device, ion implantation of a source extension and/or drain extension of the common-source device, or a halo ion implantation of the common-source device with one or more of a different ionic species, a different dosage, a different energy, or a different tilt angle than a corresponding one or more of ion implantation of a well of the common-gate device, ion implantation of a source and/or drain extension of the common-gate device, or a halo ion implantation of the common-gate device.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: August 29, 2023
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Yun Shi, Paul T. DiCarlo, Hailing Wang
  • Publication number: 20230238385
    Abstract: Silicon-on-insulator (SOI) substrate processing for transistor enhancement is disclosed. In certain embodiments, a silicon substrate for an SOI process is separated into sub-regions or islands by dielectric. Thus, the substrate is changed from having one region and one shared contact into multiple substrate sub-regions with independent contacts. Since the substrate serves as a back gate to SOI transistors formed in an active silicon layer, breaking the substrate into independent or separate islands leads to a drop in the impact of each island on the drain-to-source voltage and/or gate-to-source voltage of the SOI transistors. Accordingly, reduced harmonics and improved linearity are achieved.
    Type: Application
    Filed: January 19, 2023
    Publication date: July 27, 2023
    Inventors: Hailing Wang, Guillaume Alexandre Blin, David Scott Whitefield, Paul T. DiCarlo
  • Patent number: 11677395
    Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: June 13, 2023
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, Jerod F. Mason, David Scott Whitefield, Paul T. DiCarlo
  • Publication number: 20230084412
    Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.
    Type: Application
    Filed: August 16, 2022
    Publication date: March 16, 2023
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, Jerod F. Mason, David Scott Whitefield, Paul T. DiCarlo
  • Publication number: 20230009677
    Abstract: A field-effect transistor (FET) and a radio-frequency module are provided comprising an active region comprising a source region, a drain region, a body region disposed between the source region and the drain region, a first body extension portion in contact with the body region, a second body extension portion in contact with the body region, and a body contact region in contact with the first extension portion and the second extension portion; and a gate disposed on a top surface of the body region. A die is also provided comprising two or more such FETs.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 12, 2023
    Inventors: Hailing Wang, Guillaume Alexandre Blin, David Scott Whitefield
  • Patent number: 11418185
    Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: August 16, 2022
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, Jerod F. Mason, David Scott Whitefield, Paul T. DiCarlo
  • Publication number: 20220254812
    Abstract: SOI-based technology platforms are described that provide fully integrated front end integrated circuits (FEICs) that include switches, low-noise amplifiers (LNAs), and power amplifiers (PAs). The PAs can be built in a thick film region of the integrated circuit, resulting in a partially depleted silicon-on-insulator (PDSOI) PA, and the switches and LNAs can be built in a thin film region of the integrated circuit, resulting in fully depleted silicon-on-insulator (FDSOI) switches and LNAs. The resulting fully integrated FEIC includes PDSOI PAs with FDSOI switches and LNAs. Passive components can be built in the thick film region, the thin film region, or both regions.
    Type: Application
    Filed: November 11, 2021
    Publication date: August 11, 2022
    Inventors: Hailing Wang, Guillaume Alexandre Blin, David Scott Whitefield
  • Publication number: 20220038091
    Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.
    Type: Application
    Filed: July 13, 2021
    Publication date: February 3, 2022
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, Jerod F. Mason, David Scott Whitefield, Paul T. DiCarlo
  • Publication number: 20210335857
    Abstract: Field-effect transistor (FET) devices are described herein that include an insulator layer, a plurality of active field-effect transistors (FETs) formed from an active silicon layer implemented over the insulator layer, a substrate layer implemented under the insulator layer, and proximity electrodes for a plurality of the FETs that are each configured to receive a voltage and to generate an electric field between the proximity electrode and a region generally underneath a corresponding active FET. FET devices can be stacked wherein one or more of the FET devices in the stack includes a proximity electrode. The proximity electrodes can be biased together, biased in groups, and/or biased individually.
    Type: Application
    Filed: June 29, 2021
    Publication date: October 28, 2021
    Inventors: Hailing Wang, Hanching Fuh, Dylan Charles Bartle, Jerod F. Mason
  • Publication number: 20210265242
    Abstract: The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly. The source fingers and the drain fingers can be arranged in alternating rows.
    Type: Application
    Filed: May 11, 2021
    Publication date: August 26, 2021
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, David Scott Whitefield, Paul T. DiCarlo
  • Patent number: 11063586
    Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: July 13, 2021
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, Jerod F. Mason, David Scott Whitefield, Paul T. DiCarlo
  • Patent number: 11049890
    Abstract: Field-effect transistor (FET) devices are described herein that include an insulator layer, a plurality of active field-effect transistors (FETs) formed from an active silicon layer implemented over the insulator layer, a substrate layer implemented under the insulator layer, and proximity electrodes for a plurality of the FETs that are each configured to receive a voltage and to generate an electric field between the proximity electrode and a region generally underneath a corresponding active FET. FET devices can be stacked wherein one or more of the FET devices in the stack includes a proximity electrode. The proximity electrodes can be biased together, biased in groups, and/or biased individually.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: June 29, 2021
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Hailing Wang, Hanching Fuh, Dylan Charles Bartle, Jerod F. Mason
  • Publication number: 20210151582
    Abstract: A method of fabricating a cascode amplifier including a common-source device and a common-gate device includes performing one or more of ion implantation of a well of the common-source device, ion implantation of a source extension and/or drain extension of the common-source device, or a halo ion implantation of the common-source device with one or more of a different ionic species, a different dosage, a different energy, or a different tilt angle than a corresponding one or more of ion implantation of a well of the common-gate device, ion implantation of a source and/or drain extension of the common-gate device, or a halo ion implantation of the common-gate device.
    Type: Application
    Filed: January 4, 2021
    Publication date: May 20, 2021
    Inventors: Yun Shi, Paul T. DiCarlo, Hailing Wang
  • Patent number: 11004774
    Abstract: The fabrication of field-effect transistor (FET) devices is described herein where the FET devices include one or more body contacts implemented between source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. The FET devices can include source fingers and drain fingers interleaved with gate fingers. The source and drain fingers of a first S/G/D assembly can be electrically connected to the source and drain fingers of a second S/G/D assembly.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: May 11, 2021
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, David Scott Whitefield, Paul T. DiCarlo
  • Publication number: 20210075417
    Abstract: Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.
    Type: Application
    Filed: September 1, 2020
    Publication date: March 11, 2021
    Inventors: Hailing Wang, Dylan Charles Bartle, Hanching Fuh, Jerod F. Mason, David Scott Whitefield, Paul T. DiCarlo