Abstract: Field-effect transistor (FET) devices are described herein that include an insulator layer, a plurality of active field-effect transistors (FETs) formed from an active silicon layer implemented over the insulator layer, a substrate layer implemented under the insulator layer, and proximity electrodes for a plurality of the FETs that are each configured to receive a voltage and to generate an electric field between the proximity electrode and a region generally underneath a corresponding active FET. Switches with multiple FET devices having proximity electrodes are also disclosed.

Abstract: A cascode amplifier including a common-source device and a common-gate device formed utilizing different processing parameters to separately optimize performance of the common-source device and common-gate device.

Abstract: Field-effect transistor (FET) devices are described herein that include an insulator layer, a field-effect transistor implemented over the insulator layer, a substrate layer implemented under the insulator layer, and a proximity electrode that extends at least partially through the insulator layer and positioned from the FET by a distance that is less than about 5 ?m. The FET device can include one or more substrate contact features as well.

Abstract: Aspects of this disclosure relate to a radio frequency system that includes an envelope generator configured to generate an envelope signal corresponding to an envelope of a radio frequency signal and at least two radio frequency components coupled to the envelope generator. One of the radio frequency components is a radio frequency switch configured to pass the radio frequency signal. The radio frequency switch is configured to receive the envelope signal to cause intermodulation distortion associated with the radio frequency switch to be reduced.

Abstract: Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in parallel with an auxiliary path, both the main path and the auxiliary path having a plurality of field-effect transistors. The circuit assembly also includes a first gate bias network connected to the main path. The circuit assembly also includes a second gate bias network connected to a first subset of the plurality of FETs of the auxiliary path. The circuit assembly also includes a third gate bias network connected to a second subset of the plurality of FETs of the auxiliary path, the second gate bias network and the third gate bias network being independently configurable to improve linearity of the switching function.

Abstract: Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in parallel with an auxiliary path. The circuit assembly also includes a first gate bias network connected to the main path. The circuit assembly also includes a second gate bias network connected to the auxiliary path, the second gate bias network configured to improve linearity of the switching function.

Abstract: Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in parallel with a first auxiliary path and the main path in series with a second auxiliary path. The circuit assembly also includes a first gate bias network connected to the main path. The circuit assembly also includes a second gate bias network connected to the first auxiliary path. The circuit assembly also includes a third gate bias network connected to the second auxiliary path, the second gate bias network and the third gate bias network configured to improve linearity of the switching function.

Abstract: Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in parallel with an auxiliary path, both the main path and the auxiliary path having a plurality of field-effect transistors. The circuit assembly also includes a first gate bias network connected to the main path. The circuit assembly also includes a second gate bias network connected to a first subset of the plurality of FETs of the auxiliary path. The circuit assembly also includes a third gate bias network connected to a second subset of the plurality of FETs of the auxiliary path so that the third gate bias network switches on the auxiliary path when the main path is on for nonlinear cancellation, and switches off the auxiliary path when the main path is off to enable the branch to withstand maximum voltage swings.

Abstract: Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in series with an auxiliary path. The circuit assembly also includes a first gate bias network connected to the main path. The circuit assembly also includes a second gate bias network connected to the auxiliary path, the second gate bias network configured to improve linearity of the switching function.

Abstract: Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in parallel with an auxiliary path. The circuit assembly also includes a gate bias network connected to the main path and to the auxiliary path, the main path and the auxiliary path each having different structures that are configured to improve linearity of the switching function.

Abstract: Aspects of this disclosure relate to a radio frequency system that includes an envelope generator configured to generate an envelope signal corresponding to an envelope of a radio frequency signal and at least two radio frequency components coupled to the envelope generator. One of the radio frequency components is a radio frequency switch configured to pass the radio frequency signal. The radio frequency switch is configured to receive the envelope signal to cause intermodulation distortion associated with the radio frequency switch to be reduced.

Abstract: Aspects of this disclosure relate to a switching circuit with enhanced linearity. The switching circuit can include a switch and an envelope generator. The switch can receive an input signal, provide an output signal, and receive an envelope signal corresponding to an envelope of the input signal. The envelope generator can generate the envelope signal so as to cause intermodulation distortion in the output signal to be reduced to cause linearity of the switch to be improved.

Abstract: Field-effect transistor (FET) devices are described herein that include an insulator layer, a field-effect transistor implemented over the insulator layer, a substrate layer implemented under the insulator layer, and a proximity electrode that extends at least partially through the insulator layer and positioned from the FET by a distance that is less than about 5 ?m. The FET device can include one or more substrate contact features as well.

Abstract: Variable handle wafer resistivity for silicon-on-insulator devices. In some embodiments, a radio-frequency device can include a silicon-on-insulator substrate having an insulator layer and a handle wafer. The radio-frequency device can further include a plurality of field-effect transistors implemented over the insulator layer to cover a corresponding portion of the handle wafer having a non-uniform distribution of resistivity values.

Abstract: Field-effect transistor (FET) devices are described herein that include one or more body contacts implemented near source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. For example, body contacts can be implemented between S/G/D assemblies rather than on the ends of such assemblies. This can advantageously improve body contact influence on the S/G/D assemblies while maintaining a targeted size for the FET device.

Abstract: Variable buried oxide thickness for silicon-on-insulator devices. In some embodiments, a radio-frequency device can include a silicon-on-insulator substrate having an insulator layer and a handle wafer. The radio-frequency device can further include a plurality of field-effect transistors implemented over the insulator layer. Each transistor can be separated from the handle wafer by a corresponding portion of the insulator layer. The corresponding portion of the insulator layer can have an average thickness value such that the average thickness values associated with the plurality of FETs transistors form a non-uniform distribution.

Abstract: Field-effect transistor (FET) devices are described herein that include one or more body contacts implemented near source, gate, drain (S/G/D) assemblies to improve the influence of a voltage applied at the body contact on the S/G/D assemblies. For example, body contacts can be implemented between S/G/D assemblies rather than on the ends of such assemblies. This can advantageously improve body contact influence on the S/G/D assemblies while maintaining a targeted size for the FET device.

Abstract: A test circuit for a ring oscillator comprising a plurality of inverting stages includes a power supply, the power supply configured to provide a voltage to the plurality of inverting stages of the ring oscillator at a power output; and a power sensing resistor located between the power output of the power supply and direct current (DC) bias inputs of the inverting stages of the ring oscillator, wherein a signal from the power sensing resistor is configured to be monitored to determine a characteristic of the ring oscillator.

Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.

Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.