Patents by Inventor Hailing Wang
Hailing Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9217769Abstract: A test circuit for a ring oscillator comprising a plurality of inverting stages includes a power supply, the power supply configured to provide a voltage to the plurality of inverting stages of the ring oscillator at a power output; and a power sensing resistor located between the power output of the power supply and direct current (DC) bias inputs of the inverting stages of the ring oscillator, wherein a signal from the power sensing resistor is configured to be monitored to determine a characteristic of the ring oscillator.Type: GrantFiled: October 9, 2012Date of Patent: December 22, 2015Assignee: International Business Machines CorporationInventors: Hanyi Ding, Kai D. Feng, Hailing Wang, Zhijian Yang
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Patent number: 9058441Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.Type: GrantFiled: June 27, 2014Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Wilfried Ernest-August Haensch, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang, Richard Q. Williams
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Publication number: 20140310676Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.Type: ApplicationFiled: June 27, 2014Publication date: October 16, 2014Inventors: Wilfried Ernest-August Haensch, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang, Richard Q. Williams
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Publication number: 20140237438Abstract: A method of modeling an integrated circuit chip includes generating a model of a bond pad using a design tool running on a computer device. The method also includes connecting a first inductor, a first resistor, and a first set of parallel-resistor-inductor elements in series between a first node and a second node in the model. The method further includes connecting a second inductor, a second resistor, and a second set of parallel-resistor-inductor elements in series between the second node and a third node in the model. The first node corresponds to a first signal port of the bond pad. The second node corresponds to a second signal port of the bond pad.Type: ApplicationFiled: February 15, 2013Publication date: August 21, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hanyi DING, Kai D. FENG, Hailing WANG
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Patent number: 8806419Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.Type: GrantFiled: August 20, 2013Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Wilfried Ernest-August Haensch, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang, Richard Q. Williams
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Patent number: 8806415Abstract: A method of modeling an integrated circuit chip includes generating a model of a bond pad using a design tool running on a computer device. The method also includes connecting a first inductor, a first resistor, and a first set of parallel-resistor-inductor elements in series between a first node and a second node in the model. The method further includes connecting a second inductor, a second resistor, and a second set of parallel-resistor-inductor elements in series between the second node and a third node in the model. The first node corresponds to a first signal port of the bond pad. The second node corresponds to a second signal port of the bond pad.Type: GrantFiled: February 15, 2013Date of Patent: August 12, 2014Assignee: International Business Machines CorporationInventors: Hanyi Ding, Kai D. Feng, Hailing Wang
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Patent number: 8799848Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.Type: GrantFiled: January 15, 2013Date of Patent: August 5, 2014Assignee: International Business Machines CorporationInventors: Wilfried Ernest-August Haensch, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang, Richard Q. Williams
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Publication number: 20140201700Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.Type: ApplicationFiled: August 20, 2013Publication date: July 17, 2014Applicant: International Business Machines CorporationInventors: Wilfried Ernest-August HAENSCH, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang, Richard Q. Williams
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Publication number: 20140201699Abstract: A method for modeling FinFET width quantization is described. The method includes fitting a FinFET model of a FinFET device to single fin current/voltage characteristics. The FinFET device comprises a plurality of fins. The method includes obtaining statistical data of at least one sample FinFET device. The statistical data includes DIBL data and SS data. The method also includes fitting the FinFET model to a variation in a current to turn off the finFETs device (IOFF) in the statistical data using the DIBL data and the SS data and determining a model for a voltage to turn off the finFETs device (VOFF). The method also includes fitting the FinFET model to the VOFF.Type: ApplicationFiled: January 15, 2013Publication date: July 17, 2014Applicant: International Business Machines CorporationInventors: Wilfried Ernest-August HAENSCH, Chung-Hsun Lin, Philip J. Oldiges, Hailing Wang, Richard Q. Williams
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Publication number: 20140097858Abstract: A test circuit for a ring oscillator comprising a plurality of inverting stages includes a power supply, the power supply configured to provide a voltage to the plurality of inverting stages of the ring oscillator at a power output; and a power sensing resistor located between the power output of the power supply and direct current (DC) bias inputs of the inverting stages of the ring oscillator, wherein a signal from the power sensing resistor is configured to be monitored to determine a characteristic of the ring oscillator.Type: ApplicationFiled: October 9, 2012Publication date: April 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hanyi Ding, Kai D. Feng, Hailing Wang, Zhijian Yang
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Patent number: 8525549Abstract: A function cell comprising a first field effect transistor (FET) device, a second FET device, a first node connected to a gate terminal of the first FET device and a gate terminal of the second FET device, wherein the first node is operative to receive a voltage signal from an alternating current (AC) voltage source, an amplifier portion connected to the first FET device and the second FET device, the amplifier portion operative to receive a signal from the first FET device and the second FET device, a phase comparator portion having a first input terminal connected to an output terminal of the amplifier and a second input terminal operative to receive the voltage signal from the AC voltage source, the phase comparator portion operative to output a voltage indicative of a bit of a binary value.Type: GrantFiled: February 23, 2012Date of Patent: September 3, 2013Assignee: International Business Machines CorporationInventors: Kai D. Feng, Hailing Wang, Ping-Chuan Wang, Zhijian Yang
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Publication number: 20130222013Abstract: A function cell comprising a first field effect transistor (FET) device, a second FET device, a first node connected to a gate terminal of the first FET device and a gate terminal of the second FET device, wherein the first node is operative to receive a voltage signal from an alternating current (AC) voltage source, an amplifier portion connected to the first FET device and the second FET device, the amplifier portion operative to receive a signal from the first FET device and the second FET device, a phase comparator portion having a first input terminal connected to an output terminal of the amplifier and a second input terminal operative to receive the voltage signal from the AC voltage source, the phase comparator portion operative to output a voltage indicative of a bit of a binary value.Type: ApplicationFiled: February 23, 2012Publication date: August 29, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kai D. Feng, Hailing Wang, Ping-Chuan Wang, Zhijian Yang
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Patent number: 8514028Abstract: A voltage controlled oscillator (VCO), IC and CMOS IC including the VCO. The VCO includes an LC tank circuit, a pair of cross-coupled devices connected to the tank circuit and driving a pair of buffers. Each of the pair of cross-coupled devices includes a field effect transistor (FET) with an independently controllable body, e.g., the surface layer of a Silicon on Insulator (SOI) chip or the surface well of a multi-well chip. Diodes in the multi-well structure are biased off in each device. The tank circuit is coupled to the buffers solely through the FET drain to body capacitance.Type: GrantFiled: August 17, 2011Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Hanyi Ding, Pinping Sun, Hailing Wang
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Publication number: 20130044838Abstract: A voltage controlled oscillator (VCO), IC and CMOS IC including the VCO. The VCO includes an LC tank circuit, a pair of cross-coupled devices connected to the tank circuit and driving a pair of buffers. Each of the pair of cross-coupled devices includes a field effect transistor (FET) with an independently controllable body, e.g., the surface layer of a Silicon on Insulator (SOI) chip or the surface well of a multi-well chip. Diodes in the multi-well structure are biased off in each device.Type: ApplicationFiled: August 17, 2011Publication date: February 21, 2013Applicant: International Business Machines CorporationInventors: Hanyi Ding, Pinping Sun, Hailing Wang