Abstract: The present invention discloses a composite substrate for manufacturing an acoustic wave resonator and a Surface Acoustic Wave (SAW) resonator, and a manufacturing method thereof.

Abstract: In a method for forming a film bulk acoustic resonator (FBAR), a bulk acoustic wave (BAW) film stack (120) and a support structure (130) are successively formed on a first substrate (100). The support structure (130) includes a primary support wall (131), an isolation wall (132) internal to the primary support wall (131) and a secondary support pillar (133) internal to the isolation wall (132). After a second substrate (200) is bonded and the first substrate (100) is removed, the secondary support pillar (133) and the isolation wall (132) are removed through a release window (120a) in an area delimited by the isolation wall (132).

Abstract: A wafer-level system-in-package (WLSiP) package structure is provided. The WLSiP package structure includes a device wafer, an adhesive layer, and a plurality of second chips. The device wafer includes a first front surface having a plurality of first chips integrated therein and a first back surface opposing the first front surface. The adhesive layer is formed on the first front surface of the device wafer and the adhesive layer includes a plurality of through-holes exposing the first front surface. The plurality of second chips are bonded to the device wafer, and the plurality of second chips are bonded with the adhesive layer to cover the plurality of first through-holes in a one-to-one correspondence.

Abstract: A bulk acoustic wave resonator, a filter, and a radio frequency communication system are provided. The bulk acoustic wave resonator includes a substrate and a bottom electrode layer, where a cavity is formed therebetween. The bulk acoustic wave resonator also includes a piezoelectric layer formed on the bottom electrode layer and over the cavity, and a top electrode layer formed over the piezoelectric layer. At least one of the bottom electrode layer and the top electrode layer has a convex portion or concave portion. The convex portion is located in a region of the cavity and is protruded facing away from a bottom of the cavity, and the concave portion is located in the region of the cavity and is recessed towards the bottom of the cavity. Each of the convex portion and the concave portion is located in a peripheral region surrounding the piezoelectric layer.

Abstract: Method for fabricating a photodetector includes providing a first substrate containing pixel circuits and common electrode connection members formed therein. A first wring board material layer is formed on the first substrate and electrically connected to the pixel circuits. A second wiring board material layer is formed on a second substrate and electrically connected to the pixel layers formed therein. The first and second wiring board material layers are bonded. The second substrate, and the second and first wiring board material layers are etched to form through holes with isolation wall members formed therein, the through holes dividing the pixel layer, and the second and first wiring board material layers into pixel units, and second and first wiring boards. Each isolation wall member includes a conductive member and a sidewall between the conductive member and the pixel unit. A transparent electrode layer is formed on the second substrate.

Abstract: Photodetectors and fabrication methods thereof and imaging sensors are provided. An exemplary photodetector includes a first substrate formed with pixel circuits and common electrode connection members and first wiring boards electrically connected to the corresponding pixel circuits; and a second substrate formed with pixel units and isolation wall members isolating pixel units. Each isolation wall member includes a conductive member and a sidewall; second wiring boards are formed on a front surface of the second substrate; the second wiring boards are electrically connected to first terminals of the pixel units; a transparent electrode layer is formed on a back surface of the second substrate; and a second terminal of each pixel unit is electrically connected to the transparent electrode layer. The second wiring boards are bonded and electrically connected to the first wiring boards and the transparent electrode layer is electrically connected to the common electrode connection members.

Abstract: A packaging method and a packaging structure of a film bulk acoustic resonator are provided. The packaging method includes: providing a resonant cavity main structure including a first substrate and a film bulk acoustic resonant structure having a first cavity formed therebetween; forming a resonator cover by providing a second substrate and forming an elastic bonding material layer containing a second cavity and an initial opening; bonding the resonant cavity main structure and the resonator cover together through the elastic bonding material layer and removing elasticity of the elastic bonding material layer, where the second cavity is at least partially aligned with the first cavity; forming a through-hole containing the initial opening and a hole connected with the initial opening and passing through the resonator cover; and forming a conductive interconnection layer covering a sidewall of the through-hole and a portion of a surface of the resonator cover.

Abstract: A packaging method and a packaging structure of a film bulk acoustic resonator are provided. The packaging method includes: providing a resonant cavity main structure including a first substrate and a film bulk acoustic resonant structure having a first cavity formed therebetween; forming a resonator cover by providing a second substrate and forming an elastic bonding material layer containing a second cavity; bonding the resonant cavity main structure and the resonator cover together through the elastic bonding material layer and removing elasticity of the elastic bonding material layer, where the second cavity is at least partially aligned with the first cavity; forming a through-hole penetrating through the resonator cover and exposing a corresponding electrical connection part of the film bulk acoustic resonant structure; and forming a conductive interconnection layer on a sidewall of the through-hole and on a portion of a surface of the resonator cover.

Abstract: The present disclosure provides a packaging method and packaging structure of an FBAR. A second cavity in a resonator cover provided includes a groove in a second substrate and a space surrounded by an elastic bonding material layer. The elastic bonding material layer bonds the resonator cover to a resonant cavity main structure, and elasticity of the elastic bonding material layer is removed after the bonding. Through holes and a conductive interconnection layer on inner surfaces of the through holes are formed on the resonator cover. Since the second cavity includes the groove in the second substrate and the space surrounded by the elastic bonding material layer, which can avoid problems that performance of the elastic bonding material layer is unstable with temperature and humidity changes when the second cavity is entirely surrounded by the elastic bonding material layer, that is, the stability of the resonator is improved.

Abstract: The present disclosure provides a packaging module and packaging method of a BAW resonator. The packaging method includes: bonding a BAW resonant device including a first substrate and a resonant structure provided on the first substrate to a second substrate through a bonding layer; forming through holes exposing corresponding electrical connection portions of the resonant structure at a side of the first substrate; and forming a conductive interconnection layer on inner surfaces of the through holes and on a portion of a surface of the first substrate to avoid steps of etching through holes and depositing conductive materials from the bonding layer, so that a material of the bonding layer can be selected to provide good bonding effect, which helps to reduce the process difficulty, and improves the stability of the through holes and the formed packaging module, thereby improving the performance of the BAW resonator packaging structure.

Abstract: The present disclosure provides a wafer level packaging method and a package structure. The wafer level packaging method includes: forming a bonding structure including a device wafer and a plurality of first chips bonded to the device wafer; conformally covering the plurality of first chips and the device wafer exposed by the plurality of first chips with an insulating layer; conformally covering the insulating layer with a shielding layer; and forming an encapsulation layer on the shielding layer. The wafer level package structure includes: a device wafer; a plurality of first chips bonded to the device wafer; an insulating layer conformally covering the plurality of first chips and the device wafer exposed by the plurality of first chips; a shielding layer conformally covering the insulating layer; and an encapsulation layer formed on the shielding layer. The wafer level package structure provides a reduced volume and a reduced thickness.

Abstract: Wafer-level packaging structure is provided. First chips are bonded to the device wafer. A first encapsulation layer is formed on the device wafer, covering the first chips. The first chip includes: a chip front surface with a formed first pad, facing the device wafer; and a chip back surface opposite to the chip front surface. A first opening is formed in the first encapsulation layer to expose at least one first chip having an exposed chip back surface for receiving a loading signal. A metal layer structure is formed covering the at least one first chip, a bottom and sidewalls of the first opening, and the first encapsulation layer, followed by an alloying treatment on the chip back surface and the metal layer structure to form a back metal layer on the chip back surface.

Abstract: A wafer-level system-in-package (WLSiP) package structure is provided. The WLSiP package structure includes a device wafer, an adhesive layer, and a plurality of second chips. The device wafer includes a first front surface having a plurality of first chips integrated therein and a first back surface opposing the first front surface. The adhesive layer is formed on the first front surface of the device wafer and the adhesive layer includes a plurality of through-holes exposing the first front surface. The plurality of second chips are bonded to the device wafer, and the plurality of second chips are bonded with the adhesive layer to cover the plurality of first through-holes in a one-to-one correspondence.

Abstract: Wafer-level system-in-package packaging method and package structure are provided. The method includes: forming a bonding structure, where the bonding structure includes a device wafer and a plurality of chips bonded to the device wafer, where the plurality of chips contains one or more first chips to-be-shielded; forming an encapsulation layer covering the plurality of chips; forming a trench in the encapsulation layer to surround each first chip of the one or more first chips; and forming a conductive material in the trench and on the encapsulation layer, where the conductive material includes a shielding housing, the shielding housing including a conductive sidewall formed in the trench and a conductive layer formed on a portion of the encapsulation layer above the each first chip and connected with the conductive sidewall.

Abstract: A wafer-level package structure is provided, including a device wafer integrated with a first chip. The device wafer includes a first front surface integrated with the first chip and a first back surface opposite to the first front surface. A first oxide layer is formed on the first front surface. A second chip is provided to include a bonding surface, on which a second oxide layer is formed. A carrier substrate is provided to be temporarily bonded with the surface of the second chip that faces away from the bonding surface. The second chip is bonded with the device wafer through bonding the first and the second oxide layers using a fusion bonding process. The second chip and the carrier substrate are debonded. An encapsulation layer is formed on the first oxide layer and covers the second chip.

Abstract: Wafer-level packaging method and package structure are provided. In an exemplary method, first chips are bonded to the device wafer. A first encapsulation layer is formed on the device wafer, covering the first chips. The first chip includes: a chip front surface with a formed first pad, facing the device wafer; and a chip back surface opposite to the chip front surface. A first opening is formed in the first encapsulation layer to expose at least one first chip having an exposed chip back surface for receiving a loading signal. A metal layer structure is formed covering the at least one first chip, a bottom and sidewalls of the first opening, and the first encapsulation layer, followed by an alloying treatment on the chip back surface and the metal layer structure to form a back metal layer on the chip back surface.

Abstract: A wafer-level system-in-package (WLSiP) packaging method and a WLSiP package structure are provided. The method includes providing a device wafer including a first front surface and a first back surface and providing a plurality of second chips. The method also includes forming an adhesive layer on the first front surface and patterning the adhesive layer to form a plurality of first through-holes. In addition, the method includes bonding the plurality of second chips with a remaining adhesive layer to cover the plurality of first through-holes. Moreover, the method includes forming a plurality of second through-holes, which are connected with the plurality of first through-holes to form a plurality of first conductive through-holes, each first conductive through-hole includes a second through-hole and a first through-hole. Further, the method includes forming a first conductive plug in a first conductive through-hole to electrically connect to one of the plurality of second chips.

Abstract: A wafer-level packaging method and a package structure are provided. In the method, a first wafer is provided having first chips formed there-in. A surface of each first chip is integrated with a first electrode. A first dielectric layer is formed on the first wafer to expose each first electrode. Second chips are provided with a surface of each second chip integrated with a second electrode. A second dielectric layer is formed on the plurality of second chips to expose each second electrode. The second dielectric layer is positioned relative to the first dielectric layer. The second chips are bonded to the first wafer with each second chip aligned relative to one first chip to form a cavity there-between. A chip interconnection structure is formed in the cavity to electrically connect the first electrode with the second electrode. An encapsulation layer covers the second chips.

Abstract: A wafer-level packaging method and a package structure are provided. In the packaging method, a device wafer integrated with a first chip is provided. The device wafer includes a first front surface integrated with the first chip and a first back surface opposite to the first front surface. A first oxide layer is formed on the first front surface. A second chip is provided to include a bonding surface, on which a second oxide layer is formed. A carrier substrate is provided to be temporarily bonded with the surface of the second chip that faces away from the bonding surface. The second chip is bonded with the device wafer through bonding the first and the second oxide layers using a fusion bonding process. The second chip and the carrier substrate are debonded. An encapsulation layer is formed on the first oxide layer and covers the second chip.

Abstract: Wafer level package structures and packaging methods are provided. An exemplary method includes providing a device wafer having a first front surface and a first back surface opposing the first front surface, wherein at least one first chip is integrated in the first front surface; forming a first oxide layer on the first front surface of the device wafer; providing at least one second chip having a to-be-bonded surface; forming a second oxide layer on the to-be-bonded surface of each second chip; providing a carrier wafer; temporally bonding a surface of the second chip opposing the second oxide layer to the carrier wafer; forming an encapsulation layer on the carrier wafer between adjacent second chips of the at least one second; and bonding the device wafer and the second chip by bonding the first oxide layer with the second oxide layer by a low-temperature fusion bonding process.