Patents by Inventor Haining S. Yang

Haining S. Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9431535
    Abstract: Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. The structure includes a gate stack comprising an oxide layer, a polysilicon layer and sidewalls with adjacent spacers. The structure further includes an epitaxially grown straining material directly on the polysilicon layer and between portions of the sidewalls. The epitaxially grown straining material, in a relaxed state, strains the polysilicon layer.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: August 30, 2016
    Assignee: GLOBALFOUNDRIES INC
    Inventors: Thomas W. Dyer, Haining S. Yang
  • Patent number: 9276111
    Abstract: Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. A method of forming a semiconductor structure includes forming sidewalls and spacers adjacent to a gate stack structure, and forming a recess in the gate stack structure. The method further includes epitaxially growing a straining material on a polysilicon layer of the gate stack structure, and in the recess in the gate stack structure. The straining material is Si:C and the gate stack structure is a PFET gate stack structure. The straining material is grown above and covering a top surface of the sidewalls and the spacers.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: March 1, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Thomas W. Dyer, Haining S. Yang
  • Patent number: 9059171
    Abstract: A semiconductor fuse and methods of making the same. The fuse includes a fuse element and a compressive stress liner that reduces the electro-migration resistance of the fuse element. The method includes forming a substrate, forming a trench feature in the substrate, depositing fuse material in the trench feature, depositing compressive stress liner material over the fuse material, and patterning the compressive stress liner material.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Haining S. Yang
  • Publication number: 20150162446
    Abstract: Complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions are provided. Each CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.
    Type: Application
    Filed: October 6, 2014
    Publication date: June 11, 2015
    Inventors: Xiangdong Chen, Thomas W. Dyer, Kenneth Settlemeyer, Haining S. Yang
  • Patent number: 9040960
    Abstract: The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Xiangdong Chen, Haining S. Yang
  • Patent number: 9006836
    Abstract: A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves forming a shallow-trench-isolation oxide (STI) isolating the n-type device from the p-type device. The method further involves adjusting the shallow-trench-isolation oxide corresponding to at least one of the n-type device and the p-type device such that a thickness of the shallow-trench-isolation oxide adjacent to the n-type device is different from a thickness of the shallow-trench-isolation oxide adjacent to the p-type device, and forming a strain layer over the semiconductor substrate.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Haining S. Yang, Huilong Zhu
  • Publication number: 20150054028
    Abstract: Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. The structure includes a gate stack comprising an oxide layer, a polysilicon layer and sidewalls with adjacent spacers. The structure further includes an epitaxially grown straining material directly on the polysilicon layer and between portions of the sidewalls. The epitaxially grown straining material, in a relaxed state, strains the polysilicon layer.
    Type: Application
    Filed: October 16, 2014
    Publication date: February 26, 2015
    Inventors: Thomas W. DYER, Haining S. YANG
  • Publication number: 20150037957
    Abstract: Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. A method of forming a semiconductor structure includes forming sidewalls and spacers adjacent to a gate stack structure, and forming a recess in the gate stack structure. The method further includes epitaxially growing a straining material on a polysilicon layer of the gate stack structure, and in the recess in the gate stack structure. The straining material is Si:C and the gate stack structure is a PFET gate stack structure. The straining material is grown above and covering a top surface of the sidewalls and the spacers.
    Type: Application
    Filed: October 16, 2014
    Publication date: February 5, 2015
    Inventors: Thomas W. Dyer, Haining S. Yang
  • Patent number: 8896069
    Abstract: Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. The structure includes a gate stack comprising an oxide layer, a polysilicon layer and sidewalls with adjacent spacers. The structure further includes an epitaxially grown straining material directly on the polysilicon layer and between portions of the sidewalls. The epitaxially grown straining material, in a relaxed state, strains the polysilicon layer.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas W Dyer, Haining S Yang
  • Patent number: 8889504
    Abstract: Semiconductor devices are provided which have a tensile and/or compressive strain applied thereto and methods of manufacturing. A method of forming a semiconductor structure includes forming sidewalls and spacers adjacent to a gate stack structure, and forming a recess in the gate stack structure. The method further includes epitaxially growing a straining material on a polysilicon layer of the gate stack structure, and in the recess in the gate stack structure. The straining material is Si:C and the gate stack structure is a PFET gate stack structure. The straining material is grown above and covering a top surface of the sidewalls and the spacers.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas W Dyer, Haining S Yang
  • Patent number: 8853746
    Abstract: The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xiangdong Chen, Thomas W. Dyer, Kenneth Settlemyer, Haining S. Yang
  • Patent number: 8836044
    Abstract: An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure. NFETs that are used in the SRAM cells are exposed to oxygen during the anneal process, which alters the effective work function of the gate metal, such that the threshold voltage is increased, without the need for increasing the dopant concentration, which can adversely affect issues such as mismatch due to random dopant fluctuation, GIDL and junction leakage.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xinlin Wang, Xiangdong Chen, Haining S. Yang
  • Patent number: 8829645
    Abstract: An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Deok-Kee Kim, Ahmet S Ozcan, Haining S Yang
  • Patent number: 8809142
    Abstract: An e-fuse structure and method has an anode; a fuse link (a first end of the fuse link is connected to the anode); a cathode (a second end of the fuse link opposite the first end is connected to the cathode); and a silicide layer on the fuse link. The silicide layer has a first silicide region adjacent the anode and a second silicide region adjacent the cathode. The second silicide region comprises an impurity not contained within the first silicide region. Further, the first silicide region is thinner than the second silicide region.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Deok-Kee Kim, Ahmet S. Ozcan, Haining S. Yang
  • Patent number: 8809915
    Abstract: A gate conductor structure is provided having a barrier region between a N-type device and a P-type device, wherein the barrier region minimizes or eliminates cross-diffusion of dopant species across the barrier region. The barrier region comprises at least one sublithographic gap in the gate conductor structure. The sublithographic gap is formed by using self-assembling copolymers to form a sublithographic patterned mask over the gate conductor structure. According to one embodiment, at least one sublithographic gap is a slit or line that traverses the width of the gate conductor structure. The sublithographic gap is sufficiently deep to minimize or prevent cross-diffusion of the implanted dopant from the upper portion of the gate conductor. According to another embodiment, the sublithographic gaps are of sufficient density that cross-diffusion of dopants is reduced or eliminated during an activation anneal such that changes in Vt are minimized.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Wai-Kin Li, Haining S. Yang
  • Patent number: 8809187
    Abstract: Contact with a floating body of an FET in SOI may be formed in a portion of one of the two diffusions of the FET, wherein the portion of the diffusion (such as N?, for an NFET) which is “sacrificed” for making the contact is a portion of the diffusion which is not immediately adjacent (or under) the gate. This works well with linked body FETs, wherein the diffusion does not extend all the way to BOX, hence the linked body (such as P?) extends under the diffusion where the contact is being made. An example showing making contact for ground to two NFETs (PG and PD) of a 6T SRAM cell is shown.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 19, 2014
    Assignee: International Business Machines Corporation
    Inventors: Yue Tan, Zhibin Ren, Richard A. Wachnik, Haining S. Yang
  • Patent number: 8796854
    Abstract: A hybrid interconnect structure (of the single or dual damascene type) is provided in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance. Moreover, the hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Thomas M. Shaw, Keith Kwong Hon Wong, Haining S. Yang
  • Patent number: 8765558
    Abstract: A CMOS structure and a method for fabricating the CMOS structure include within a semiconductor substrate a first gate located over a first active region of a first polarity and a second gate located over a second active region of a second polarity different than the first polarity. The first active region and the second active region are separated by an isolation region. The first gate and the second gate are co-linear, with facing endwalls that terminate over the isolation region. The facing endwalls do not have a spacer located or formed adjacent or adjoining thereto, although sidewalls of the first gate and the second gate do. The CMOS structure may be fabricated using a sequential replacement gate method.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Haining S. Yang
  • Patent number: 8754526
    Abstract: A hybrid interconnect structure is provided that includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance. Moreover, the hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Thomas M. Shaw, Keith Kwong Hon Wong, Haining S. Yang
  • Patent number: 8753979
    Abstract: A method of forming a hybrid interconnect structure including dielectric spacers is provided. The method includes forming at least one opening in a dielectric material utilizing a patterned hard mask located on a surface of the dielectric material as a mask, wherein an undercut is present beneath said patterned hard mask. Next, a dense dielectric spacer is formed in the at least one opening and at least partially on exposed sidewalls of the dielectric material. A diffusion barrier and a conductive material are then formed within the at least one opening.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chih-Chao Yang, Thomas M. Shaw, Keith Kwong Hon Wong, Haining S. Yang