Abstract: Provided are a method, an apparatus and a device for obstacle in lane warning. The method includes receiving information of an obstacle in a front lane of a first vehicle, where the first vehicle is in front of a second vehicle; and performing an obstacle warning on the second vehicle according to the information of the obstacle. The second vehicle receives the information of the obstacle, and performs the obstacle warning on the second vehicle according to the information of the obstacle to prevent the second vehicle from failing to detect the obstacle in a blind area when the sight of the second vehicle is blocked by the first vehicle; the front vehicle notifies the subsequent vehicle of the obstacle in the lane immediately, which facilitates the driver to handle the situation in advance, improves the vehicle's ability to sense the obstacle and prevents the collision from occurring.

Abstract: Embodiments of the present disclosure provide a method, an apparatus and a device for an illegal vehicle warning. The method includes: detecting an illegal vehicle in a preset area; and performing the illegal vehicle warning on a target vehicle entering the preset area according to vehicle information of a detected illegal vehicle in the preset area. In the embodiments of the present disclosure, the traffic control unit detects the illegal vehicle in the preset area, and the illegal vehicle warning is performed on the target vehicle entering the preset area according to the vehicle information of the detected illegal vehicle in the preset area, thereby avoiding or mitigating the collision of the target vehicle with the illegal vehicle, and improving the traffic safety of the target vehicle.

Abstract: An electronic device that coordinates a playback operation is described. In particular, an interface circuit in the electronic device may calculate, based on differences between transmit times when packets were transmitted by a second electronic device and receive times of the packets, relative drift as a function of time between a clock in the interface circuit and a second clock in the second electronic device. Then, the interface circuit may adjust, based on the relative drift, a clock circuit that provides the clock to eliminate the relative drift, and may determine a remaining time offset between the clock and the second clock. Next, the interface circuit may modify a future time when the electronic device is to perform the playback operation based on the remaining time offset to determine a corrected future time, and the electronic device may perform the playback operation at the corrected future time.

Abstract: An electronic device that coordinates a playback operation is described. In particular, an interface circuit in the electronic device may calculate, based on differences between transmit times when packets were transmitted by a second electronic device and receive times of the packets, relative drift as a function of time between a clock in the interface circuit and a second clock in the second electronic device. Then, the interface circuit may adjust, based on the relative drift, a clock circuit that provides the clock to eliminate the relative drift, and may determine a remaining time offset between the clock and the second clock. Next, the interface circuit may modify a future time when the second electronic device is to perform the playback operation based on the remaining time offset to determine a corrected future time, and may transmit information to the second electronic device specifying the corrected future time.

Abstract: An electronic device that reduces relative drift is described. In particular, an interface circuit in the electronic device may calculate, based on differences between transmit times when packets were transmitted by a second electronic device and receive times of the packets, relative drift as a function of time between a clock in the interface circuit and a second clock in the second electronic device. Then, the interface circuit may adjust, based on the relative drift, a clock circuit that provides the clock to eliminate the relative drift, and may store the adjustments to the clock circuit. Furthermore, when a wireless reset occurs, the interface circuit may adapt the clock circuit based on the stored adjustments to reduce the relative drift while the interface circuit restores frequency lock with the second clock based on additional packets with additional transmit times that are received from the second electronic device.

Abstract: An electronic device that coordinates a playback operation is described. In particular, an interface circuit in the electronic device may calculate, based on differences between transmit times when packets were transmitted by a second electronic device and receive times of the packets, relative drift as a function of time between a clock in the interface circuit and a second clock in the second electronic device. Then, the interface circuit may adjust, based on the relative drift, a clock circuit that provides the clock to eliminate the relative drift, and may determine a remaining time offset between the clock and the second clock. Next, the interface circuit may modify a future time when the electronic device is to perform the playback operation based on the remaining time offset to determine a corrected future time, and the electronic device may perform the playback operation at the corrected future time.

Abstract: A multiplying delay-locked loop circuit includes a delay chain including a plurality of variable delay circuits connected in series and having a delay chain output, and a feedback loop including circuitry for deriving a digital control signal representing magnitude and sign of phase offset in the delay chain output, for controlling delay in ones of the variable delay circuits. The circuitry for deriving a digital control signal includes a sampling time-to-digital converter (STDC) configured to operate on a time delay between inputs to generate the digital control signal. The STDC subtracts a second difference the signals derived from the delay chain output and output of the feedback divider from a first difference between the signals derived from the delay chain output and output of the feedback divider to provide a difference value, and the difference value indicates sign and magnitude of output offset in the delay chain output.

Abstract: A processor in an electronic device may coordinate an interface clock in the electronic device with a second interface clock in a second electronic device based on time-coordination information received in packets from the second electronic device. Then, the processor captures timing information associated with the interface clock provided by an interface clock circuit to increase a resolution of a system clock. Moreover, the processor may track, using the timing information, relative drift as a function of time between the system clock and the interface clock, and may determine, based on the relative drift, an estimated time offset between the interface clock and the system clock at the future time. Next, the processor modifies a future time when the electronic device is to perform the playback operation based on the estimated time offset to determine a corrected future time, and may perform the playback operation at the corrected future time.

Abstract: A processor in an electronic device maintains coordination between a system clock provided by a system clock circuit and an interface clock provided by a clock circuit. Then, the processor may calculate, based on differences between transmit times when packets were transmitted by a second electronic device and receive times of the packets, relative drift as a function of time between the interface clock and a second interface clock in the second electronic device. Moreover, the processor adjusts, based on the relative drift, the system clock circuit to eliminate the relative drift. Next, the processor may determine a remaining time offset between the interface clock and the second interface clock. Furthermore, the processor modifies a future time when the electronic device is to perform the playback operation based on the remaining time offset to determine a corrected future time, and may perform the playback operation at the corrected future time.

Abstract: An electronic device that reduces relative drift is described. In particular, an interface circuit in the electronic device may calculate, based on differences between transmit times when packets were transmitted by a second electronic device and receive times of the packets, relative drift as a function of time between a clock in the interface circuit and a second clock in the second electronic device. Then, the interface circuit may adjust, based on the relative drift, a clock circuit that provides the clock to eliminate the relative drift, and may store the adjustments to the clock circuit. Furthermore, when a wireless reset occurs, the interface circuit may adapt the clock circuit based on the stored adjustments to reduce the relative drift while the interface circuit restores frequency lock with the second clock based on additional packets with additional transmit times that are received from the second electronic device.

Abstract: A processor in an electronic device may coordinate an interface clock in the electronic device with a second interface clock in a second electronic device based on time-coordination information received in packets from the second electronic device. Then, the processor captures timing information associated with the interface clock provided by an interface clock circuit to increase a resolution of a system clock. Moreover, the processor may track, using the timing information, relative drift as a function of time between the system clock and the interface clock, and may determine, based on the relative drift, an estimated time offset between the interface clock and the system clock at the future time. Next, the processor modifies a future time when the electronic device is to perform the playback operation based on the estimated time offset to determine a corrected future time, and may perform the playback operation at the corrected future time.

Abstract: A processor in an electronic device maintains coordination between a system clock provided by a system clock circuit and an interface clock provided by a clock circuit. Then, the processor may calculate, based on differences between transmit times when packets were transmitted by a second electronic device and receive times of the packets, relative drift as a function of time between the interface clock and a second interface clock in the second electronic device. Moreover, the processor adjusts, based on the relative drift, the system clock circuit to eliminate the relative drift. Next, the processor may determine a remaining time offset between the interface clock and the second interface clock. Furthermore, the processor modifies a future time when the electronic device is to perform the playback operation based on the remaining time offset to determine a corrected future time, and may perform the playback operation at the corrected future time.

Abstract: An electronic device that coordinates a playback operation is described. In particular, an interface circuit in the electronic device may calculate, based on differences between transmit times when packets were transmitted by a second electronic device and receive times of the packets, relative drift as a function of time between a clock in the interface circuit and a second clock in the second electronic device. Then, the interface circuit may adjust, based on the relative drift, a clock circuit that provides the clock to eliminate the relative drift, and may determine a remaining time offset between the clock and the second clock. Next, the interface circuit may modify a future time when the electronic device is to perform the playback operation based on the remaining time offset to determine a corrected future time, and the electronic device may perform the playback operation at the corrected future time.

Abstract: An electronic device that coordinates a playback operation is described. In particular, an interface circuit in the electronic device may calculate, based on differences between transmit times when packets were transmitted by a second electronic device and receive times of the packets, relative drift as a function of time between a clock in the interface circuit and a second clock in the second electronic device. Then, the interface circuit may adjust, based on the relative drift, a clock circuit that provides the clock to eliminate the relative drift, and may determine a remaining time offset between the clock and the second clock. Next, the interface circuit may modify a future time when the second electronic device is to perform the playback operation based on the remaining time offset to determine a corrected future time, and may transmit information to the second electronic device specifying the corrected future time.

Abstract: An analog fractional-N phase-locked loop includes an oscillator loop having a reference input, a feedback input, and a loop output, and a fractional feedback divider configured to divide signals on the loop output by a divisor. Output of the fractional feedback divider is fed back to the feedback input. A compensation circuit is coupled to, and configured to apply a time delay to, the reference input or the feedback input, to compensate for delay introduced by the fractional feedback divider. The compensation circuit may be a digital-to-time converter configured to convert a digital delay signal into the time delay. The digital-to-time converter may be coupled to the reference input to delay signals to match feedback delay introduced by the fractional feedback divider, or to the feedback input to subtract the time delay to cancel feedback delay introduced by the fractional feedback divider.

Abstract: A multiplying delay-locked loop circuit includes a delay chain including a plurality of variable delay circuits connected in series and having a delay chain output, and a feedback loop including circuitry for deriving a digital control signal representing magnitude and sign of phase offset in the delay chain output, for controlling delay in ones of the variable delay circuits. The circuitry for deriving a digital control signal includes a sampling time-to-digital converter (STDC) configured to operate on a time delay between inputs to generate the digital control signal. The STDC subtracts a second difference the signals derived from the delay chain output and output of the feedback divider from a first difference between the signals derived from the delay chain output and output of the feedback divider to provide a difference value, and the difference value indicates sign and magnitude of output offset in the delay chain output.

Abstract: A digital phase locked loop (DPLL) circuit includes a digital-to-time converter (DTC) configured to generate a delayed reference clock signal by delaying a reference clock signal according to a delay control signal and a time-to-digital converter (TDC) coupled to an output of the DTC. The TDC is configured to sample a value of a transition signal according to the delayed reference clock signal and to generate an output signal indicating a phase difference between the delayed clock signal and an input clock signal. A method of controlling a DPLL includes delaying a reference clock signal according to a delay control signal, sampling a value of a transition signal according to the delayed reference clock signal, generating an output signal indicating a phase difference between the delayed clock signal and an input clock signal, and generating a digitally controlled oscillator (DCO) clock signal according to the output signal.

Abstract: A digital phase locked loop (DPLL) circuit includes a digital-to-time converter (DTC) configured to generate a delayed reference clock signal by delaying a reference clock signal according to a delay control signal and a time-to-digital converter (TDC) coupled to an output of the DTC. The TDC is configured to sample a value of a transition signal according to the delayed reference clock signal and to generate an output signal indicating a phase difference between the delayed clock signal and an input clock signal. A method of controlling a DPLL includes delaying a reference clock signal according to a delay control signal, sampling a value of a transition signal according to the delayed reference clock signal, generating an output signal indicating a phase difference between the delayed clock signal and an input clock signal, and generating a digitally controlled oscillator (DCO) clock signal according to the output signal.

Abstract: A processor for a cable television set-top box has an interface for coupling the processor to a second processor. The processor also has a port that is coupleable to control a tuner, a demodulator and a DOCSIS module with or without DSG support. The tuner has an output coupled to the demodulator input, and the demodulator has an output to the DOCSIS module input. The demodulator's output is also coupled to a conditional access module controlled by the second processor. The processor issues commands via the port to control at least one of the tuner and the demodulator based on instructions received via the interface from the second processor.

Abstract: A nitrogen compound luminescent material belongs to the field of LED inorganic luminescent materials. The nitrogen compound luminescent material has a chemical formula: M1-yEuyAlSiCxN3-4/3x. In the formula, M represents one or several of Li, Mg, Ca, Sr and Ba; 0<x?0.2, 0<y?0.5; and C represents the element Carbon. The luminescent material can be excited by ultraviolet, near ultraviolet or blue excitation light source such as LED, and emits red light with wavelength between 500-800nm, especially the maximum emission wavelength between 600-700 nm, exhibiting a wider excitation spectrum range, efficiency and stability. The corresponding method of the preparation is simple, easy to mass production and pollution-free. By using the luminescence material, and with ultraviolet, near ultraviolet or blue LED and other luminescent materials such as green fluorescent powder, a white LED light source can be provided.