Patents by Inventor Haiting Wang

Haiting Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11075268
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: July 27, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Jiehui Shu, Baofu Zhu, Haiting Wang, Sipeng Gu
  • Publication number: 20210225406
    Abstract: Disclosed is a video acquisition method. The method includes acquiring at least two existing video segments selected by a user through a video selection interface, where the video selection interface is an interface which is switched from a video capture interface or a detail interface; and synthesizing the at least two existing video segments into a target video that has a duration less than or equal to a preset video duration based on the preset video duration. Further disclosed are a video acquisition device, a terminal and a storage medium.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 22, 2021
    Inventors: Xu HAN, Haiting WANG, Pingfei FU
  • Publication number: 20210217887
    Abstract: A transistor device that includes a single semiconductor structure having an outer perimeter and a vertical height, wherein the single semiconductor structure is at least partially defined by a trench formed in a semiconductor substrate and a first layer of material positioned on the bottom surface of the trench and around the outer perimeter of the single semiconductor structure. The device also includes a second layer of material positioned on the first layer of material and around the outer perimeter of the single semiconductor structure, a gap between the outer perimeter of the single semiconductor structure and both the first and second layers of material (when considered collectively) and an insulating sidewall spacer positioned in the gap, wherein the insulating sidewall spacer has a vertical height that is less than the vertical height of the single semiconductor structure.
    Type: Application
    Filed: January 10, 2020
    Publication date: July 15, 2021
    Inventors: Jiehui Shu, Haiting Wang, Hong Yu
  • Patent number: 11062715
    Abstract: An audio encoding and decoding method and a related apparatus are provided. The audio encoding method may include: determining a coding mode of a current frame; when determining that the coding mode of the current frame is an anticorrelated signal coding mode, performing time-domain downmix processing on left and right channel signals in the current frame by using a time-domain downmix processing manner corresponding to the anticorrelated signal coding mode, to obtain a primary channel signal and a secondary channel signal, where the time-domain downmix processing manner corresponding to the anticorrelated signal coding mode is a time-domain downmix processing manner corresponding to an anticorrelated signal channel combination scheme, and the anticorrelated signal channel combination scheme is a channel combination scheme corresponding to a near out of phase signal; and encoding the obtained primary channel signal and secondary channel signal in the current frame.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: July 13, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Haiting Li, Bin Wang, Lei Miao
  • Patent number: 11043566
    Abstract: A semiconductor device is provided that includes a substrate, an active region, a pair of gates, a plurality of semiconductor structures and a plurality of pillar structures. The active region is over the substrate. The pair of gates is formed over the active region, and each gate of the pair of gates includes a gate structure and a pair of spacer structures disposed on sidewalls of the gate structure. The plurality of semiconductor structures is arranged between the pair of gates in an alternating arrangement configuration having a first width and a second width. The first width is substantially equal to a width of the gate structure. The plurality of semiconductor structures is separated by the plurality of pillar structures.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: June 22, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Jiehui Shu, Judson Robert Holt, Sipeng Gu, Haiting Wang
  • Patent number: 11037600
    Abstract: Disclosed are a video processing method and apparatus, a terminal and a medium. The method includes acquiring a first editing parameter of a playback speed of a continuous video and a second editing parameter of a playback speed of each of at least one target video segment, where the continuous video is synthesized from at least two video segments and the at least one target video segment includes at least one of the at least two video segments; calculating a target playback speed of each of the at least two video segments according to the first editing parameter and the second editing parameter corresponding to the each of the at least one target video segment; and synthesizing, based on the target playback speed of the each of the at least two video segments, the at least two video segments into a target video conforming to a preset duration.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: June 15, 2021
    Assignee: Beijing Microlive Vision Technology Co., Ltd.
    Inventors: Xu Han, Haiting Wang, Pingfei Fu
  • Patent number: 11037821
    Abstract: Methods of forming interconnects and structures for interconnects. A hardmask layer is patterned to form a plurality of first trenches arranged with a first pattern, and sidewall spacers are formed inside the first trenches on respective sidewalls of the hardmask layer bordering the first trenches. An etch mask is formed over the hardmask layer. The etch mask includes an opening exposing a portion of the hardmask layer between a pair of the sidewall spacers. The portion of the hardmask layer exposed by the opening in the etch mask is removed to define a second trench in the hardmask layer.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: June 15, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Xiaoming Yang, Haiting Wang, Hong Yu, Jeffrey Chee, Guoliang Zhu
  • Patent number: 11018221
    Abstract: A semiconductor device is provided, which includes an active region, a first structure, a second gate structure, a first gate dielectric sidewall, a second gate dielectric sidewall, a first air gap region, a second air gap region and a contact structure. The active region is formed over a substrate. The first and second gate structures are formed over the active region and between the first gate structure and the second gate structure are the first gate dielectric sidewall, the first air gap region, the contact structure, the second air gap region and a second gate dielectric sidewall.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: May 25, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Chun Yu Wong, Haiting Wang, Yong Jun Shi, Xiaoming Yang, Liu Jiang
  • Publication number: 20210151581
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 20, 2021
    Inventors: Haiting WANG, Hong YU, Zhenyu HU
  • Patent number: 11004748
    Abstract: This disclosure relates to a method of fabricating semiconductor devices with a gate-to-gate spacing that is wider than a minimum gate-to-gate spacing and the resulting semiconductor devices. The method includes forming gate structures over an active structure, the gate structures including a first gate structure, a second gate structure, and a third gate structure. The second gate structure is between the first and third gate structures. A plurality of epitaxial structures are formed adjacent to the gate structures, wherein the second gate structure separates two epitaxial structures and the two epitaxial structures are between the first and third gate structures. The second gate structure is removed. A conductive region is formed to connect the epitaxial structures between the first and third gate structures.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: May 11, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Sipeng Gu, Jiehui Shu, Haiting Wang
  • Publication number: 20210111261
    Abstract: A semiconductor device is provided that includes a substrate, an active region, a pair of gates, a plurality of semiconductor structures and a plurality of pillar structures. The active region is over the substrate. The pair of gates is formed over the active region, and each gate of the pair of gates includes a gate structure and a pair of spacer structures disposed on sidewalls of the gate structure. The plurality of semiconductor structures is arranged between the pair of gates in an alternating arrangement configuration having a first width and a second width. The first width is substantially equal to a width of the gate structure. The plurality of semiconductor structures is separated by the plurality of pillar structures.
    Type: Application
    Filed: October 10, 2019
    Publication date: April 15, 2021
    Inventors: JIEHUI SHU, JUDSON ROBERT HOLT, SIPENG GU, HAITING WANG
  • Publication number: 20210111264
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 15, 2021
    Inventors: Jiehui SHU, Sipeng GU, Haiting WANG
  • Publication number: 20210111065
    Abstract: A method and related structure provide a void-free dielectric over trench isolation region in an FDSOI substrate. The structure may include a first transistor including a first active gate over the substrate, a second transistor including a second active gate over the substrate, a first liner extending over the first transistor, and a second, different liner extending over the second transistor. A trench isolation region electrically isolates the first transistor from the second transistor. The trench isolation region includes a trench isolation extending into the FDSOI substrate and an inactive gate over the trench isolation. A dielectric extends over the inactive gate and in direct contact with an upper surface of the trench isolation region. The dielectric is void-free, and the liners do not extend over the trench isolation.
    Type: Application
    Filed: October 9, 2019
    Publication date: April 15, 2021
    Inventors: Yongjun Shi, Wei Hong, Chun Yu Wong, Haiting Wang, Liu Jiang
  • Patent number: 10971625
    Abstract: A semiconductor device is provided, which includes an array of active regions, gate stacks and substantially uniform epitaxial structures. The gate stacks of the array include a first gate stack and a second gate stack over an active region. An active pillar between the first gate stack and the second gate stack, and the active pillar separating two substantially uniform epitaxial structures. A contact structure over the active pillar, positioned equidistant from the first gate stack and the second gate stack.
    Type: Grant
    Filed: June 30, 2019
    Date of Patent: April 6, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Michael V Aquilino, Daniel Jaeger, Man Gu, Bradley Morgenfeld, Haiting Wang, Kavya Sree Duggimpudi, Wang Zheng
  • Publication number: 20210098591
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to air spacer structures and methods of manufacture. The structure includes: a plurality of gate structures comprising active regions; contacts extending to the active regions; a plurality of anchor structures between the active regions; and air spacer structures adjacent to the contacts.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Inventors: Julien FROUGIER, Ali RAZAVIEH, Haiting WANG
  • Patent number: 10937693
    Abstract: At least one method, apparatus and system disclosed herein involves forming local interconnect regions during semiconductor device manufacturing. A plurality of fins are formed on a semiconductor substrate. A gate region is over a portion of the fins. A trench silicide (TS) region is formed adjacent a portion of the gate region. The TS region comprises a first TS metal feature and a second TS metal feature. A bi-layer self-aligned contact (SAC) cap is formed over a first portion of the TS region and electrically coupled to a portion of the gate region. A portion of the bi-layer SAC cap is removed to form a first void. A first local interconnect feature is formed in the first void.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: March 2, 2021
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Andreas Knorr, Haiting Wang, Hui Zang
  • Patent number: 10937685
    Abstract: The present disclosure generally relates to semiconductor devices and processing. The present disclosure also relates to isolation structures formed in active regions, more particularly, diffusion break structures in an active semiconductor layer of a semiconductor device. The present disclosure also relates to methods of forming such structures and replacement metal gate processes.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 2, 2021
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sipeng Gu, Haiting Wang, Jiehui Shu
  • Publication number: 20210050412
    Abstract: A semiconductor device is provided, which includes an active region, a first structure, a second gate structure, a first gate dielectric sidewall, a second gate dielectric sidewall, a first air gap region, a second air gap region and a contact structure. The active region is formed over a substrate. The first and second gate structures are formed over the active region and between the first gate structure and the second gate structure are the first gate dielectric sidewall, the first air gap region, the contact structure, the second air gap region and a second gate dielectric sidewall.
    Type: Application
    Filed: August 12, 2019
    Publication date: February 18, 2021
    Inventors: Chun Yu WONG, Haiting Wang, Yong Jun Shi, Xiaoming Yang, Liu Jiang
  • Publication number: 20210050419
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.
    Type: Application
    Filed: August 15, 2019
    Publication date: February 18, 2021
    Inventors: Jiehui Shu, Baofu Zhu, Haiting Wang, Sipeng Gu
  • Publication number: 20210043766
    Abstract: A laterally diffused metal-oxide semiconductor (LDMOS) device is disclosed. The LDMOS FET includes a gate structure between a source region and a drain region over a p-type semiconductor substrate; and a trench isolation partially under the gate structure and between the gate structure and the drain region. A p-well is under and adjacent the source region; and an n-well is under and adjacent the drain region. A counter doping region abuts and is between the p-well and the n-well, and is directly underneath the gate structure. The counter doping region increases drain-source breakdown voltage compares to conventional approaches.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Inventors: Baofu Zhu, Shesh Mani Pandey, Jiehui Shu, Sipeng Gu, Haiting Wang