Patents by Inventor Haiting Wang

Haiting Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190273148
    Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.
    Type: Application
    Filed: May 17, 2019
    Publication date: September 5, 2019
    Inventors: Wei Zhao, Haiting Wang, David P. Brunco, Jiehui Shu, Shesh Mani Pandey, Jinping Liu, Scott Beasor
  • Patent number: 10403742
    Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 3, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Wei Zhao, Haiting Wang, David P. Brunco, Jiehui Shu, Shesh Mani Pandey, Jinping Liu, Scott Beasor
  • Patent number: 10396206
    Abstract: A method of manufacturing a semiconductor device includes the formation of an oxide spacer layer to modify the critical dimension of a gate cut opening in connection with a replacement metal gate process. The oxide spacer layer is deposited after etching a gate cut opening in an overlying hard mask such that the oxide spacer layer is deposited onto sidewall surfaces of the hard mask within the opening and directly over the top surface of a sacrificial gate. The oxide spacer may also be deposited into recessed regions within an interlayer dielectric located adjacent to the sacrificial gate. By filling the recessed regions with an oxide, the opening of trenches through the oxide spacer layer and the interlayer dielectric to expose source/drain junctions can be simplified.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: August 27, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ashish Kumar Jha, Haiting Wang, Wei Hong, Wei Zhao, Tae Jeong Lee, Zhenyu Hu
  • Publication number: 20190259668
    Abstract: Structures and fabrication methods for a field-effect transistor. First and second spacers are formed adjacent to opposite sidewalls of a gate structure. A section of the gate structure is partially removed with a first etching process to form a cut that extends partially through the gate structure. After partially removing the section of the gate structure with the first etching process, upper sections of the first and second sidewall spacers arranged above the gate structure inside the cut are at least partially removed. After at least partially removing the upper sections of the first and second sidewall spacers, the section of the gate structure is completely removed from the cut with a second etching process. A dielectric material is deposited inside the cut to form a dielectric pillar.
    Type: Application
    Filed: February 20, 2018
    Publication date: August 22, 2019
    Inventors: Chang Seo Park, Haiting Wang, Shimpei Yamaguchi, Junsic Hong, Yong Mo Yang, Scott Beasor
  • Patent number: 10388652
    Abstract: The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yongiun Shi, Lei Sun, Laertis Economikos, Ruilong Xie, Lars Liebmann, Chanro Park, Daniel Chanemougame, Min Gyu Sung, Hsien-Ching Lo, Haiting Wang
  • Publication number: 20190244865
    Abstract: One illustrative integrated circuit product disclosed herein includes a first final gate structure for a first transistor device, a second final gate structure for a second transistor device, the first and second transistors having a gate width direction and a gate length direction that is substantially normal to the gate width direction, and an insulating gate separation structure positioned between the first and second final gate structures, the insulating gate separation structure comprising an upper portion and a lower portion, the lower portion having a first lateral width in the gate width direction that is substantially uniform throughout a vertical height of the lower portion, the upper portion having a substantially uniform second lateral width in the gate width direction that is substantially uniform throughout a vertical height of the upper portion, wherein the second lateral width is less than the first lateral width.
    Type: Application
    Filed: September 18, 2018
    Publication date: August 8, 2019
    Inventors: Guowei Xu, Hui Zang, Haiting Wang, Yue Zhong
  • Patent number: 10373877
    Abstract: One illustrative method disclosed herein includes forming a plurality of transistors on a semiconductor substrate, wherein each of the transistors comprise source/drain epitaxial semiconductor material in the source/drain regions, a contact etch stop layer (CESL) positioned above the source/drain epitaxial semiconductor material and an insulating material positioned above the contact etch stop layer, and forming a plurality of contact isolation cavities by performing at least one etching process sequence, wherein the etching process sequence is adapted to sequentially remove the insulating material, the CESL and the source/drain epitaxial semiconductor material, and forming a contact isolation structure in each of the contact isolation cavities.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: August 6, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Haiting Wang, Hong Yu, Hui Zang, Wei Zhao, Yue Zhong, Guowei Xu, Laertis Economikos, Jerome Ciavatti, Scott Beasor
  • Patent number: 10373875
    Abstract: Methods of fabricating structures that include contacts coupled with a source/drain region of a field-effect transistor. Source/drain regions are formed adjacent to a temporary gate structure. In one process, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions, followed by deposition of a fill material, replacement of the temporary gate structure with a functional gate structure, and removal of the fill material. In another process, the fill material is formed first and the temporary gate structure is replaced by a functional gate structure; following removal of the fill material, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions. A conductive layer having separate portions contacting the separate source/drain regions is formed, with the dielectric pillar separating the portions of the conductive layer.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 6, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Daniel Jaeger, Chanro Park, Laertis Economikos, Haiting Wang, Hui Zang
  • Publication number: 20190229183
    Abstract: A methodology for forming a single diffusion break structure in a FinFET device involves localized, in situ oxidation of a portion of a semiconductor fin. Fin oxidation within a fin cut region may be preceded by the formation of epitaxial source/drain regions over the fin, as well as by a gate cut module, where portions of a sacrificial gate that straddle the fin are replaced by an isolation layer. Localized oxidation of the fin enables the stress state in adjacent, un-oxidized portions of the fin to be retained, which may beneficially impact carrier mobility and hence conductivity within channel portions of the fin.
    Type: Application
    Filed: January 19, 2018
    Publication date: July 25, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Haiting WANG, Hui ZANG, Chun Yu WONG, Kwan-Yong LIM
  • Patent number: 10361289
    Abstract: A method of thermally oxidizing a Si fin to form an oxide layer over the Si fin and then forming an ALD oxide layer over the oxide layer and resulting device are provided. Embodiments include forming a plurality of Si fins on a Si substrate; forming a dielectric layer over the plurality of Si fins and the Si substrate; recessing the dielectric layer, exposing a top portion of the plurality of Si fins; thermally oxidizing surface of the top portion of the plurality of Si fins, an oxide layer formed; and forming an ALD oxide layer over the oxide layer.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 23, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Zhao, Shahab Siddiqui, Haiting Wang, Ting-Hsiang Hung, Yiheng Xu, Beth Baumert, Jinping Liu, Scott Beasor, Yue Zhong, Shesh Mani Pandey
  • Publication number: 20190221661
    Abstract: A method of forming isolation pillars for a gate structure, the method including: providing a preliminary structure including a substrate having a plurality of fins thereon, an STI formed between adjacent fins, an upper surface of the STIs extending higher than an upper surface of the fins, and a hardmask over the upper surface of the fins and between adjacent STIs; forming a first trench in a first selected STI and between adjacent fins in a gate region, and forming a second trench in a second selected STI and between adjacent fins in a TS region; and filling the first and second trenches with an isolation fill thereby forming a first isolation pillar in the gate region and a second isolation pillar in the TS region, the first and second isolation pillars extending below the upper surface of the STIs.
    Type: Application
    Filed: January 12, 2018
    Publication date: July 18, 2019
    Inventors: Wei Zhao, Ming Hao Tang, Haiting Wang, Rui Chen, Yuping Ren, Hui Zang, Scott H. Beasor, Ruilong Xie
  • Publication number: 20190214308
    Abstract: Integrated circuit devices include trenches in a material layer that divide the material layer into fins. With such devices, an insulator partially fills the trenches and contacts the material layer. The top surface of the insulator (e.g., the surface opposite where the insulator contacts the material layer) has a convex dome shape between at least two of the fins. The dome shape has a first thickness from (from the bottom of the trench) where the insulator contacts the fins, and a second thickness that is greater than the first thickness where the insulator is between the fins. Further, there is a maximum thickness difference between the first and second thicknesses at the midpoint between the fins (e.g., the highest point of the dome shape is at the midpoint between the fins). Also, the top surface of the first insulator has concave divots where the first insulator contacts the fins.
    Type: Application
    Filed: January 11, 2018
    Publication date: July 11, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Yiheng Xu, Haiting Wang, Qun Gao, Scott Beasor, Kyung Bum Koo, Ankur Arya
  • Patent number: 10325811
    Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. A plurality of sacrificial layers are formed on a dielectric layer. An opening is formed that includes a first section that extends through the sacrificial layers and a second section that extends through the dielectric layer. A semiconductor material is epitaxially grown inside the opening to form a fin. The first section of the opening has a first width dimension, and the second section of the opening has a second width dimension that is less than the first width dimension.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: June 18, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: David P. Brunco, Wei Zhao, Haiting Wang
  • Publication number: 20190148373
    Abstract: The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.
    Type: Application
    Filed: November 14, 2017
    Publication date: May 16, 2019
    Inventors: Yongiun Shi, Lei Sun, Laertis Economikos, Ruilong Xie, Lars Liebmann, Chanro Park, Daniel Chanemougame, Min Gyu Sung, Hsien-Ching Lo, Haiting Wang
  • Publication number: 20190131177
    Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. A plurality of sacrificial layers are formed on a dielectric layer. An opening is formed that includes a first section that extends through the sacrificial layers and a second section that extends through the dielectric layer. A semiconductor material is epitaxially grown inside the opening to form a fin. The first section of the opening has a first width dimension, and the second section of the opening has a second width dimension that is less than the first width dimension.
    Type: Application
    Filed: October 26, 2017
    Publication date: May 2, 2019
    Inventors: David P. Brunco, Wei Zhao, Haiting Wang
  • Publication number: 20190109197
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.
    Type: Application
    Filed: October 9, 2017
    Publication date: April 11, 2019
    Inventors: Haiting WANG, Wei ZHAO, Hui ZANG, Hong YU, Zhenyu HU, Scott BEASOR, Erik GEISS, Jerome CIAVATTI, Jae Gon LEE
  • Patent number: 10249616
    Abstract: One illustrative method disclosed herein includes, among other things, forming first and second adjacent gates above a semiconductor substrate, each of the gates comprising a gate structure and a gate cap, forming a conductive resistor structure between the first and second adjacent gates, the conductive resistor structure having an uppermost surface that is positioned at a level that is below a level of an uppermost surface of the gate caps of the first and second adjacent gates, and forming first and second separate conductive resistor contact structures, each of which is conductively coupled to the conductive resistor structure.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Manfred Eller, Haiting Wang, Daniel Jaeger
  • Publication number: 20190097019
    Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.
    Type: Application
    Filed: September 22, 2017
    Publication date: March 28, 2019
    Inventors: Wei Zhao, Haiting Wang, David P. Brunco, Jiehui Shu, Shesh Mani Pandey, Jinping Liu, Scott Beasor
  • Publication number: 20190035633
    Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure formed of first dielectric material extending into the substrate. The conventional STI structure undergoes further processing, including removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride layer is formed above remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses. The nitride layer provides an “inner spacer” between the first insulating material and the second insulating material and also separates the substrate from the second insulating material.
    Type: Application
    Filed: July 31, 2017
    Publication date: January 31, 2019
    Inventors: Ashish Kumar Jha, Hui Zhan, Hong Yu, Zhenyu Hu, Haiting Wang, Edward Reis, Charles Vanleuvan
  • Patent number: 10192746
    Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure formed of first dielectric material extending into the substrate. The conventional STI structure undergoes further processing, including removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride layer is formed above remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses. The nitride layer provides an “inner spacer” between the first insulating material and the second insulating material and also separates the substrate from the second insulating material.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: January 29, 2019
    Assignee: Globalfoundries Inc.
    Inventors: Ashish Kumar Jha, Hui Zhan, Hong Yu, Zhenyu Hu, Haiting Wang, Edward Reis, Charles Vanleuvan