Abstract: One illustrative IC product disclosed herein includes an (SOI) substrate comprising a base semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer. In this particular example, the IC product also includes a first region of localized high resistivity formed in the base semiconductor layer, wherein the first region of localized high resistivity has an electrical resistivity that is greater than an electrical resistivity of the material of the base semiconductor layer. The IC product also includes a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer.

Abstract: An integrated circuit (IC) structure includes a long channel (LC) gate structure over a long channel region, the LC gate structure having a first gate height; and a short channel (SC) gate structure over a short channel region, the SC gate structure having a second gate height. The short channel region is shorter in length than the long channel region. The second gate height of the SC gate structure is no larger than the first gate height of the LC gate structure.

Abstract: One illustrative device disclosed herein includes a semiconductor substrate and a bipolar junction transistor (BJT) device that comprises a collector region, a base region and an emitter region. In this example, the device also includes a field effect transistor and at least one base conductive contact structure that conductively and physically contacts the base region.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to air spacer structures and methods of manufacture. The structure includes: a plurality of gate structures comprising active regions; contacts extending to the active regions; a plurality of anchor structures between the active regions; and air spacer structures adjacent to the contacts.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned contacts and methods of manufacture. The structure includes: adjacent diffusion regions located within a substrate material; sidewall structures above an upper surface of the substrate material, aligned on sides of the adjacent diffusion regions; and a contact between the sidewall structures and extending to within the substrate material between and in electrical contact with the adjacent diffusion regions.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a channel region in a semiconductor body. The gate structure has a first side surface and a second side surface opposite the first side surface. A first source/drain region is positioned adjacent to the first side surface of the gate structure and a second source/drain region is positioned adjacent to the second side surface of the gate structure. The first source/drain region includes a first epitaxial semiconductor layer, and the second source/drain region includes a second epitaxial semiconductor layer. A first top surface of the first epitaxial semiconductor layer is positioned at a first distance from the channel region, a second top surface of the second epitaxial semiconductor layer is positioned at a second distance from the channel region, and the first distance is greater than the second distance.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a scheme of active and dummy fin structures and methods of manufacture. The structure includes: an active fin structure; at least one dummy fin structure running along at least one side of the active fin structure along its length; a fin cut separating the at least one dummy fin structure along its longitudinal axes; and a gate structure extending over the active fin structure and the fin cut.

Abstract: One illustrative IC product disclosed herein includes an (SOI) substrate comprising a base semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer. In this particular example, the IC product also includes a first region of localized high resistivity formed in the base semiconductor layer, wherein the first region of localized high resistivity has an electrical resistivity that is greater than an electrical resistivity of the material of the base semiconductor layer. The IC product also includes a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.

Abstract: Disclosed is a video acquisition method. The method includes acquiring at least two existing video segments selected by a user through a video selection interface, where the video selection interface is an interface which is switched from a video capture interface or a detail interface; and synthesizing the at least two existing video segments into a target video that has a duration less than or equal to a preset video duration based on the preset video duration. Further disclosed are a video acquisition device, a terminal and a storage medium.

Abstract: A transistor device that includes a single semiconductor structure having an outer perimeter and a vertical height, wherein the single semiconductor structure is at least partially defined by a trench formed in a semiconductor substrate and a first layer of material positioned on the bottom surface of the trench and around the outer perimeter of the single semiconductor structure. The device also includes a second layer of material positioned on the first layer of material and around the outer perimeter of the single semiconductor structure, a gap between the outer perimeter of the single semiconductor structure and both the first and second layers of material (when considered collectively) and an insulating sidewall spacer positioned in the gap, wherein the insulating sidewall spacer has a vertical height that is less than the vertical height of the single semiconductor structure.

Abstract: A semiconductor device is provided that includes a substrate, an active region, a pair of gates, a plurality of semiconductor structures and a plurality of pillar structures. The active region is over the substrate. The pair of gates is formed over the active region, and each gate of the pair of gates includes a gate structure and a pair of spacer structures disposed on sidewalls of the gate structure. The plurality of semiconductor structures is arranged between the pair of gates in an alternating arrangement configuration having a first width and a second width. The first width is substantially equal to a width of the gate structure. The plurality of semiconductor structures is separated by the plurality of pillar structures.

Abstract: Disclosed are a video processing method and apparatus, a terminal and a medium. The method includes acquiring a first editing parameter of a playback speed of a continuous video and a second editing parameter of a playback speed of each of at least one target video segment, where the continuous video is synthesized from at least two video segments and the at least one target video segment includes at least one of the at least two video segments; calculating a target playback speed of each of the at least two video segments according to the first editing parameter and the second editing parameter corresponding to the each of the at least one target video segment; and synthesizing, based on the target playback speed of the each of the at least two video segments, the at least two video segments into a target video conforming to a preset duration.

Abstract: Methods of forming interconnects and structures for interconnects. A hardmask layer is patterned to form a plurality of first trenches arranged with a first pattern, and sidewall spacers are formed inside the first trenches on respective sidewalls of the hardmask layer bordering the first trenches. An etch mask is formed over the hardmask layer. The etch mask includes an opening exposing a portion of the hardmask layer between a pair of the sidewall spacers. The portion of the hardmask layer exposed by the opening in the etch mask is removed to define a second trench in the hardmask layer.

Abstract: A semiconductor device is provided, which includes an active region, a first structure, a second gate structure, a first gate dielectric sidewall, a second gate dielectric sidewall, a first air gap region, a second air gap region and a contact structure. The active region is formed over a substrate. The first and second gate structures are formed over the active region and between the first gate structure and the second gate structure are the first gate dielectric sidewall, the first air gap region, the contact structure, the second air gap region and a second gate dielectric sidewall.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.

Abstract: This disclosure relates to a method of fabricating semiconductor devices with a gate-to-gate spacing that is wider than a minimum gate-to-gate spacing and the resulting semiconductor devices. The method includes forming gate structures over an active structure, the gate structures including a first gate structure, a second gate structure, and a third gate structure. The second gate structure is between the first and third gate structures. A plurality of epitaxial structures are formed adjacent to the gate structures, wherein the second gate structure separates two epitaxial structures and the two epitaxial structures are between the first and third gate structures. The second gate structure is removed. A conductive region is formed to connect the epitaxial structures between the first and third gate structures.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure.

Abstract: A semiconductor device is provided that includes a substrate, an active region, a pair of gates, a plurality of semiconductor structures and a plurality of pillar structures. The active region is over the substrate. The pair of gates is formed over the active region, and each gate of the pair of gates includes a gate structure and a pair of spacer structures disposed on sidewalls of the gate structure. The plurality of semiconductor structures is arranged between the pair of gates in an alternating arrangement configuration having a first width and a second width. The first width is substantially equal to a width of the gate structure. The plurality of semiconductor structures is separated by the plurality of pillar structures.