Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes an emitter having a raised portion, a collector having a raised portion, and a base having a base layer and an extrinsic base layer stacked with the base layer. The base layer and the extrinsic base layer are positioned in a lateral direction between the raised portion of the emitter and the raised portion of the collector, the base layer has a first width in the lateral direction, the extrinsic base layer has a second width in the lateral direction, and the second width is greater than the first width.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes a lateral bipolar junction transistor including an extrinsic base region and a bilayer dielectric spacer on sidewalls of the extrinsic base region, and a p-n junction positioned under the bilayer dielectric spacer between the extrinsic base region and at least an emitter region.

Abstract: Disclosed is a semiconductor structure including a lateral heterojunction bipolar transistor (HBT). The structure includes a substrate (e.g., a silicon substrate), an insulator layer on the substrate, and a semiconductor layer (e.g., a silicon germanium layer) on the insulator layer. The structure includes a lateral HBT with three terminals including a collector, an emitter, and a base, which is positioned laterally between the collector and the emitter and which can include a silicon germanium intrinsic base region for improved performance. Additionally, the collector and/or the emitter includes: a first region, which is epitaxially grown within a trench that extends through the semiconductor layer and the insulator layer to the substrate; and a second region, which is epitaxially grown on the first region. The connection(s) of the collector and/or the emitter to the substrate effectively form thermal exit path(s) and minimize self-heating. Also disclosed is a method for forming the structure.

Abstract: A disclosed structure includes a fin-based bipolar junction transistor (BJT) with reduced base resistance. The BJT includes one or more semiconductor fins. Each semiconductor fin has opposing sidewalls, a first width, and a base recess, which extends across the first width through the opposing sidewalls. The BJT includes a base region positioned laterally between collector and emitter regions. The base region includes a base semiconductor layer (e.g., an intrinsic base layer), which fills the base recess and which has a second width greater than the first width such that the base semiconductor layer extends laterally beyond the opposing sidewalls. In a BJT with multiple semiconductor fins, the base recess on each semiconductor fin is filled with a discrete base semiconductor layer. The base region further includes an additional base semiconductor layer (e.g., an extrinsic base layer) covering the base semiconductor layer(s). Also disclosed is a method of forming the structure.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a collector having a raised portion, an emitter having a raised portion, and a base laterally arranged between the raised portion of the emitter and the raised portion of the collector. The base includes an intrinsic base layer and an extrinsic base layer stacked with the intrinsic base layer. The structure further includes a stress liner positioned to overlap with the raised portion of the collector, the raised portion of the emitter, and the extrinsic base layer.

Abstract: Embodiments of the disclosure provide a lateral bipolar transistor with a base layer of varying horizontal thickness, and related methods to form the same. A lateral bipolar transistor may include an emitter/collector (E/C) layer on a semiconductor layer. A first base layer is on the semiconductor layer and horizontally adjacent the E/C layer. The first base layer has a lower portion having a first horizontal width from the E/C layer. The first base layer also has an upper portion on the lower portion, with a second horizontal width from the E/C layer greater than the first horizontal width. A second base layer is on the first base layer and adjacent a spacer. The upper portion of the first base layer separates a lower surface of the second base layer from the E/C layer.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.

Abstract: Structures for a single diffusion break and methods of forming a structure for a single diffusion break. A cut is formed in a semiconductor fin. A single diffusion break includes a first dielectric layer in the cut and a second dielectric layer over the first dielectric layer. The first dielectric layer is comprised of a first material, and the second dielectric layer is comprised of a second material having a different composition than the first material. The second dielectric layer includes a first portion over the first dielectric layer and a second portion over the first portion. The first portion of the second dielectric layer has a first horizontal dimension, and the second portion of the second dielectric layer has a second horizontal dimension that is greater than the first horizontal dimension.

Abstract: An illustrative transistor device disclosed herein includes a gate structure positioned around a portion of a fin defined in a semiconductor substrate and epitaxial semiconductor material positioned on the fin in a source/drain region of the transistor device, wherein the epitaxial semiconductor material has a plurality of lower angled surfaces. In this example, the device further includes a first sidewall spacer positioned adjacent the gate structure, wherein a first portion of the first sidewall spacer is also positioned on and in physical contact with at least a portion of the lower angled surfaces of the epitaxial semiconductor material.

Abstract: A subtitle information display method includes: when an editing operation of a user for initial subtitle information of video information is detected, determining a video display region and an edited subtitle display region in an application display page; if the subtitle display region is not a subregion in the video display region, determining a first extension length and a first extension direction for each edge length of the video display region based on region information of the video display region and region information of the subtitle display region; extend the video display region within a region range corresponding to the application display page, based on the first extension length and the first extension direction, so that the extended video display region includes the subtitle display region; and displaying edited subtitle information in the subtitle display region.

Abstract: A transistor device disclosed herein includes, among other things, a gate electrode positioned above a semiconductor material region, a sidewall spacer positioned adjacent the gate electrode, a gate insulation layer having a first portion positioned between the gate electrode and the semiconductor material region and a second portion positioned between a lower portion of the sidewall spacer and the gate electrode along a portion of a sidewall of the gate electrode, an air gap cavity located between the sidewall spacer and the gate electrode and above the second portion of the gate insulation layer, and a gate cap layer positioned above the gate electrode, wherein the gate cap layer seals an upper end of the air gap cavity so as to define an air gap positioned adjacent the gate electrode.

Abstract: A structure includes a semiconductor fin on a substrate. A first fin transistor (finFET) is on the substrate, and a second finFET is on the substrate adjacent the first finFET. The first finFET and the second finFET include respective pairs of source/drain regions with each including a first dopant of a first polarity. An electrical isolation structure is in the semiconductor fin between one of the source/drain regions of the first finFET and one of the source/drain regions for the second FinFET, the electrical isolation structure including a second dopant of an opposing, second polarity. The electrical isolation structure extends to an upper surface of the semiconductor fin. A related method is also disclosed.

Abstract: One illustrative IC product disclosed herein includes a transistor device formed on a semiconductor substrate, the transistor device comprising a gate structure comprising an upper surface, a polish-stop sidewall spacer positioned adjacent the gate structure, wherein, at a location above an upper surface of the semiconductor substrate, when viewed in a cross-section taken through the first polish-stop sidewall spacer in a direction corresponding to a gate length direction of the transistor, an upper surface of the gate structure is substantially coplanar with an upper surface of the polish-stop sidewall spacer.

Abstract: One illustrative memory cell disclosed herein includes at least one layer of insulating material having a first opening and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer includes a spacer opening. The memory cell also includes a bottom electrode positioned within the spacer opening, a memory state material positioned above an upper surface of the bottom electrode and above an upper surface of the internal sidewall spacer, and a top electrode positioned above the memory state material.

Abstract: The invention provides a floor determination method for terminal devices, including the steps: S1: generate the atmospheric pressure data of the datum floor; S2: divide the coordinate system of a map and establish city-level grid atmospheric pressure database; S3: add commercial label to the grid data; S4: add the datum atmospheric pressure and floor-height atmospheric pressure difference to each grid; S5: judge the floor according to the device atmospheric pressure. The advantages of this invention include: it puts forward the determination method of building floor originally and can accurately calculate the floor where the device is according to the testing data of atmospheric pressure and device sensor, and the whole process of the method is fast, intelligent and accurate.

Abstract: This invention provides an IP positioning method & unit, computer storage medium and computing device. The method includes collecting the plurality of GPS coordinates pointing to the same IP address and mapping them to one coordinate system; clustering the plurality of GPS coordinates based on the K-means clustering algorithm to acquire minimum one principal cluster circle, wherein, the GPS coordinates are the principal cluster objects of the principal cluster circles; selecting the principal cluster circle with the largest number of cluster objects as the target cluster circle; screening the target cluster object from the principal clustering objects in the target cluster circle based on the preset rules and taking the GPS coordinate of the target cluster object as the IP center coordinate of the IP address.

Abstract: This invention provides an application preference text classification method based on TextRank, including the steps as follows: generate keywords of each App according to the TextRank algorithm to form a first keywords stock; indicate a seed keyword for each sub-category according to the plurality of sub-categories; get the Apps including the seek keywords from the first keywords stock by fuzzy searching according to the seed keywords and indicate such Apps with sub-categories; conduct full calculation for the seek keywords of all Apps under the sub-categories by the TextRank algorithm and generate the second keywords stock under a plurality of sub-categories; traverse the list of Apps again and compare the contents of each keyword with the second keywords stock in the similarity of character strings; if the similarity is lower than the preset threshold, delete the association between the Apps and the current sub-categories.

Abstract: A non-uniform base width bipolar junction transistor (BJT) device includes: a semiconductor substrate, the semiconductor substrate having an upper surface; and a BJT device, the BJT device comprising a collector region, a base region, and an emitter region positioned in the semiconductor substrate, the base region being positioned between the collector region and the emitter region; the base region comprising a top surface and a bottom surface, wherein a first width of the top surface of the base region in a base width direction of the BJT device is greater than a second width of the bottom surface of the base region in the base width direction of the BJT device.

Abstract: A transistor device that includes a single semiconductor structure having an outer perimeter and a vertical height, wherein the single semiconductor structure is at least partially defined by a trench formed in a semiconductor substrate and a first layer of material positioned on the bottom surface of the trench and around the outer perimeter of the single semiconductor structure. The device also includes a second layer of material positioned on the first layer of material and around the outer perimeter of the single semiconductor structure, a gap between the outer perimeter of the single semiconductor structure and both the first and second layers of material (when considered collectively) and an insulating sidewall spacer positioned in the gap, wherein the insulating sidewall spacer has a vertical height that is less than the vertical height of the single semiconductor structure.