Abstract: A gene SiFAD2-1 controlling the oleic acid content trait in sesame and its SNP marker SiSNPFAD2-1 are provided. This gene is located on chromosome 4 of sesame and belongs to an incomplete dominant control gene; compared with a wild-type allele Sifad2-1. The high oleic acid mutant gene SiFAD2-1 has a 100% explanation value for a mutant trait of sesame high oleic acid mutant HO995 (i.e., this gene controls a high oleic acid phenotype). The present application can provide a certain theoretical basis for studying the regulation mechanism of high oil acid in sesame and other crops, and also provide a material basis and genetic resources for developing molecular assisted breeding technology for sesame, breeding new varieties with high oleic acid in sesame and even other crops.

Abstract: A gene SiPT1 regulating a sesame plant architecture trait and a detection primer pair thereof are provided. This gene is located on 10th chromosome of sesame, belongs to a dominant control gene, has 100% explanation ratio for a branching trait; the gene has a length of 1318 bp, contains 4 exons and 3 introns, and its base sequence is shown in SEQ ID No. 1. Based on analysis and research of this gene, a good technical foundation can be laid for an early identification and rapid screening of sesame plant architecture in new varieties breeding; it has important technical significance for accelerating to breed new sesame varieties suitable for mechanized operations; can also provide a certain genetic foundation for the development of molecular assisted breeding technology and screening and breeding of new sesame varieties with different plant architectures.

Abstract: A sesame shattering resistance trait regulation gene Sihec3 and its application are provided. This gene is located on the third chromosome of sesame, is a recessive control gene, and fully explains the phenotypic variation of the shattering resistance trait. Genetic analysis of the shattering trait was conducted with F2 and F2:3 populations derived from a hybrid combination between a shattering resistance mutant M7 and normal shattering material. The research indicates that the seed shattering resistance trait in the tested population is a recessive trait controlled by a single gene. Based on the self-constructed sesame genome fine map and efficient gene mapping technology, the key gene Sihec3 and its allele SiHEC3 regulating the sesame shattering trait were cloned and compared. A corresponding gene marker named SSR1 for the sesame shattering resistance trait was dig. This invention provides a technical foundation for breeding new sesame varieties with shattering resistance trait.

Abstract: A detection method includes: obtaining a decision feedback equalizer coefficient, where the decision feedback equalizer coefficient includes a tap coefficient; obtaining a decision signal sequence of a decision feedback equalizer; determining a first location of a decision signal of a start of burst error in the decision signal sequence when the tap coefficient is less than or equal to a first preset threshold; and determining a second location of a decision signal of an end of burst error in the decision signal sequence based on the first location.

Abstract: The present disclosure provides an application log coding output method, a device, a system, and a computer readable storage medium. The method comprises: loading a conversion appender using an extension mechanism of a native logger, loading a log converter and a native appender for outputting a log message using the conversion appender, the log converter comprising one or more log sub-converters, and loading the log sub-converters specified by an initialization parameter using the log converter; receiving the log message sent by the native logger using the conversion appender, scheduling the log sub-converters specified by the initialization parameter to execute log coding, and sending the processed log to the native appender for secure output. By using the method, diversified log coding output can be achieved without retrofitting an application, and the method is more friendly to developers.

Abstract: An electronic device is provided. The electronic device includes a first device body, a second device body, a flexible display screen, a shaft component, and a connecting rod mechanism. The first device body is rotatably connected to the second device body via the shaft component. The connecting rod mechanism is connected to the first device body and the shaft component, respectively. The flexible display screen includes a first display screen on the first device body, a second display screen on the second device body, and a third display screen connected to the first display screen and the second display screen. In a folding process of the electronic device, the shaft component drives the first device body to approach the shaft component via the connecting rod mechanism. In an unfolding process of the electronic device, the shaft component drives the first device body to move away from the shaft component.

Abstract: A semiconductor structure and its fabrication method. First sacrificial layers are formed on a base substrate. Channel structures are formed on the first sacrificial layers. Each channel structure includes stacked channel stack layer(s). Each channel stack layer includes a second sacrificial layer and a channel layer. Dummy gate structures crossing the channel structures are also formed on the base substrate. Etching resistance of the first sacrificial layers is smaller than etching resistance of the second sacrificial layers. The channel structures and the first sacrificial layers on two sides of each dummy gate structure are removed to form first grooves. The first sacrificial layers at the bottoms of the channel structures are removed to form second grooves connected to the first grooves. Isolation layers are formed in the second grooves; and source-drain doping layers are formed in the first grooves.

Abstract: The present application relates to a multi fluid path selector valve, including a valve body, and several fluid outlet pipes. The valve body is provided with several layers of branch channels therein, the branch channel includes a fluid inlet hole and several branch holes. The valve body is provided with communication holes therein for one-to-one communicating the branch holes with the fluid outlet pipes. The valve body is provided with a control mechanism to control the on or off state between the branch hole and communication hole, and the valve body is provided with fluid inlet pipes in communication with the fluid inlet holes respectively.

Abstract: A pipetting device includes a portal frame. The portal frame is arranged with a bearing device for bearing a feed pump, a driving mechanism for driving the bearing device to move up and down, and a liquid suction and injection mechanism for sucking or injecting liquid by the feed pump. The bearing device includes a bearing plate with receiving grooves. The driving mechanism includes a first bracing plate connected to the bearing plate, and the frame is arranged with a first motor. The liquid suction and injection mechanism includes a second bracing plate. The first bracing plate is arranged with a second motor. The first motor and the second motor are connected to a PLC.

Abstract: A signal decision equalization method and apparatus are provided. The method includes: obtaining an input signal; determining a decision circuit of the input signal; obtaining a first group of decision thresholds and a first group of equalization expectations of the decision circuit; determining a decision value of the input signal based on the first group of equalization expectations, the first group of decision thresholds, and the input signal, and outputting the decision value; updating, based on the decision value and the input signal, a first equalization expectation that is in the first group of equalization expectations and that corresponds to the decision value to a second equalization expectation to obtain a second group of equalization expectations; and updating at least one decision threshold in the first group of decision thresholds based on the second equalization expectation to obtain a second group of decision thresholds.

Abstract: Semiconductor structure and method of forming semiconductor structure are provided. The semiconductor structure includes a substrate, a first isolation structure, and a first nanostructure and a second nanostructure on two sides of the first isolation structure. The semiconductor structure also includes a second isolation structure, and a third nanostructure and a fourth nanostructure on two sides of the second isolation structure. A top of the second isolation structure is lower than a top of the first isolation structure. The semiconductor structure also includes a first gate structure and a second gate structure. The first gate structure and the second gate structure expose a top surface of the first isolation structure. The semiconductor structure also includes a third gate structure and a fourth gate structure. The third gate structure and the fourth gate structure are in contact with each other on a top surface of the second isolation structure.

Abstract: The present application relates to a photon measuring and reading device, which belongs to the field of detection equipment, including a mounting seat and a photon counter. The photon counter can move up and down on the mounting seat. The mounting seat is provided with a vertically arranged sliding trough, and the photon counter is provided with a sliding rod slidably connected with the sliding trough. A double head motor is arranged on the mounting base, and a linkage mechanism is arranged between the output shaft at the tail end of the double head motor and the sliding rod. The bottom end of the photon counter is fixed with a box body.

Abstract: A semiconductor structure includes a substrate that includes a base, a plurality of channel layers on the base, and an isolation layer between each of the channel layers. The semiconductor structure also includes a gate on the substrate, spanning a top and a portion of sidewalls of the channel layers. The semiconductor structure also includes a sidewall structure on sidewalls at two sides of the gate, a source/drain region in the substrate at two sides of the gate and the sidewall structure, a source/drain electrical connection layer on the source/drain region, and an isolation structure between the source/drain electrical connection layer and the gate. The isolation structure includes a cavity, including a first cavity region and a second cavity region located on the first cavity region. A width of the second cavity region is smaller than a width of the first cavity region.

Abstract: Semiconductor structures and fabrication methods thereof are provided. The method may include providing a to-be-etched layer; forming a plurality of core layers on the to-be-etched layer, wherein a first opening and a second opening are formed between different adjacent core layers and a width of the first opening is smaller than a width of the second opening; forming a first sacrificial material layer on the to-be-etched layer and the plurality of core layers; forming a second sacrificial layer on a portion of the first sacrificial material layer in the first opening to form a sacrificial structure in the first opening; removing the plurality of core layers after forming the sacrificial structure; forming sidewall spacers on sidewall surfaces of the sacrificial structure after removing the plurality of core layers; and removing the sacrificial structure after forming the sidewall spacers.

Abstract: The present disclosure provides a method and a device for transaction clearing. The method includes receiving first clearing requests transmitted by a quantity N of terminals, where N>1; according to the first clearing requests, acquiring transaction data of the quantity N of terminals from a database; initializing a cache queue, and loading the transaction data into the cache queue; reading the transaction data in the cache queue, and performing a clearing process on the transaction data; and writing a clearing result into the database and feeding back the terminals with an execution result of the first clearing requests.

Abstract: Semiconductor structure and method of forming semiconductor structure are provided. The semiconductor structure includes a substrate, a first isolation structure, and a first nanostructure and a second nanostructure on two sides of the first isolation structure. The semiconductor structure also includes a second isolation structure, and a third nanostructure and a fourth nanostructure on two sides of the second isolation structure. A top of the second isolation structure is lower than a top of the first isolation structure. The semiconductor structure also includes a first gate structure and a second gate structure. The first gate structure and the second gate structure expose a top surface of the first isolation structure. The semiconductor structure also includes a third gate structure and a fourth gate structure. The third gate structure and the fourth gate structure are in contact with each other on a top surface of the second isolation structure.

Abstract: Semiconductor structure and formation method are provided. A method of forming a semiconductor structure includes providing a dielectric layer on a substrate, the dielectric layer including a first region and a second region under the first region, the first region including discrete first initial nanowires, and the second region including discrete second initial nanowires; etching the dielectric layer and the first initial nanowires in the first region to form a first opening in the first region, and forming first nanowires from the first initial nanowires; etching the dielectric layer at a bottom of the first opening and the second initial nanowires to form a second opening in the second region, and forming second nanowires from the second initial nanowires; forming a second source/drain layer in the second opening; forming an isolation layer on the second source/drain layer; and forming a first source/drain layer in the first opening.

Abstract: Semiconductor structure and fabrication method are provided. The semiconductor structure includes a substrate, including a first region and a second region; a plurality of fins, formed on the first region of the substrate; a first isolation structure, formed on the first region between adjacent fins and on the second region of the substrate; a second isolation structure, formed in each fin and in the first isolation structure, over the first region of the substrate; and a power rail, formed in the isolation structure and partially in the substrate of the second region.

Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a target etching layer; sequentially forming an initial mask layer, an anti-reflection layer, and a patterned structure on the target etching layer; performing a first etching process on the anti-reflection layer to remove a surface portion of the anti-reflection layer using the patterned structure as a mask; performing a surface treatment process on the patterned structure; and performing a second etching process on the anti-reflection layer until exposing a surface of the initial mask layer.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, having a plurality of fins on a surface of the substrate; a gate structure across the plurality of fins. The gate structure is located on a portion of a top surface and sidewall surfaces of the plurality of fins. The gate structure includes a first region and a second region on the first region. A bottom boundary of the second region is higher than the top surface of the plurality of fins. A size of the first region in an extending direction of the plurality of fins is smaller than a size of the second region in the extending direction of the plurality of fins.