Patents by Inventor Haiyang Zhang
Haiyang Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10714343Abstract: A semiconductor structure and a method for forming the same are provided.Type: GrantFiled: October 15, 2019Date of Patent: July 14, 2020Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International CorporationInventors: Zhuofan Chen, Haiyang Zhang
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Publication number: 20200219992Abstract: Semiconductor structure and method of forming a semiconductor structure are provided. A substrate is provided, including a first region and a second region that are adjacent to each other and arranged in a first direction. Fins are disposed on a surface of the substrate at the first region, and first openings are located between adjacent fins. The fins include fins to-be-removed. A first dielectric layer is formed on sidewalls of the fins. The first dielectric layer fills the first openings. A first groove is formed in the substrate at the second region by etching the substrate at the second region using the first dielectric layer as a mask. After forming the first groove, a second groove is formed in the substrate at the first region by removing the fins to-be-removed and a portion of the substrate located at bottoms of the fins to-be-removed.Type: ApplicationFiled: January 8, 2020Publication date: July 9, 2020Inventors: Shiliang JI, Haiyang ZHANG
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Publication number: 20200105907Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method may include: providing a semiconductor structure, where the semiconductor structure includes a semiconductor fin and an interlayer dielectric layer covering the semiconductor fin, the interlayer dielectric layer having an opening exposing a part of the semiconductor fin; forming a data storage layer at a bottom portion and a side surface of the opening; and filling a conductive material layer in the opening on the data storage layer. The present disclosure facilitate the manufacturing process of the semiconductor device and improves processing compatibility with the CMOS technology.Type: ApplicationFiled: December 3, 2019Publication date: April 2, 2020Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Zhuofan CHEN, Haiyang ZHANG
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Patent number: 10522651Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method may include: providing a semiconductor structure, where the semiconductor structure includes a semiconductor fin and an interlayer dielectric layer covering the semiconductor fin, the interlayer dielectric layer having an opening exposing a part of the semiconductor fin; forming a data storage layer at a bottom portion and a side surface of the opening; and filling a conductive material layer in the opening on the data storage layer. The present disclosure facilitate the manufacturing process of the semiconductor device and improves processing compatibility with the CMOS technology.Type: GrantFiled: November 27, 2017Date of Patent: December 31, 2019Assignees: Semiconductor Manufacturing International (Shanghai) Corp., Semiconductor Manufacturing International (Beijing) Corp.Inventors: Zhuofan Chen, Haiyang Zhang
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Patent number: 10503616Abstract: Systems and methods for replicating data from a production server to a backup server include recording at least one operation on one or more data items stored in a volume of a production server. The operation may be recorded as at least one journal event in a memory. A determination may then be made regarding whether a system malfunction incident has occurred in the production server and if so, a first set of journal events may be transferred from the memory to an auxiliary storage at a first time instant. At a second time instant, a second set of journal events recorded in the memory between the first and second time instants may be transferred to the auxiliary storage. At one journal event stored in the auxiliary storage unit may then be sent for replication to a backup server.Type: GrantFiled: February 22, 2017Date of Patent: December 10, 2019Assignee: CA, Inc.Inventors: Xiaopin Wang, Haiyang Zhang, Shaorong Li
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Publication number: 20190363097Abstract: A flash memory device and its manufacturing method, which is related to semiconductor techniques. The flash memory device comprises: a substrate; and a memory unit on the substrate, comprising: a channel structure on the substrate, wherein the channel structure comprise, in an order from inner to outer of the channel structure, a channel layer, an insulation layer wrapped around the channel layer, and a charge capture layer wrapped around the insulation layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure, wherein there exist cavities between neighboring gate structures; a support structure supporting the gate structures; and a plurality of gate contact components each contacting a gate structure. The cavities between neighboring gate structures lower the parasitic capacitance, reduce inter-gate interference, and suppress the influence from writing or erasing operations of nearby memory units.Type: ApplicationFiled: August 8, 2019Publication date: November 28, 2019Inventors: Rongyao CHANG, Zhuofan CHEN, Haiyang ZHANG
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Publication number: 20190360146Abstract: A steam spray head includes a main body and a panel fixedly connected with the main body. The panel is provided with multiple steam orifices, and the main body is provided with a cavity, a cover plate sealing the cavity and provided with a water inlet pipe and a heating element fixed at the bottom of the cavity. The panel is provided with a first chamber communicating with the steam orifices, and an opening of the first chamber is sealed by lateral walls of the main body. One side of the main body provided with the panel is provided with a steam passage communicating the cavity with the first chamber, and multiple steam jet tubes, each end of which extends into the first chamber and presses against a corresponding steam orifice to interface with the latter, and the other end of which communicates with the cavity of the main body.Type: ApplicationFiled: January 18, 2019Publication date: November 28, 2019Inventors: Shengwan Huang, Qijin Fan, Haiyang Zhang
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Publication number: 20190305108Abstract: A semiconductor device includes a substrate and a fin structure. The fin structure includes a first semiconductor layer on the substrate, and a stack of one or more semiconductor layer structures. Each of the semiconductor layer structures includes a first insulator layer and a second semiconductor layer on the first insulator layer, the first and second semiconductor layers having a same semiconductor compound.Type: ApplicationFiled: June 20, 2019Publication date: October 3, 2019Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Haiyang Zhang, Yan Wang
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Patent number: 10410920Abstract: A semiconductor structure includes a semiconductor substrate having fins and gate structures on the fins. A protective layer is formed on top surfaces of the gate structures. Sidewall spacers are formed on side surfaces of the gate structures and the protective layer. A first dielectric layer is formed on the surface of the semiconductor substrate and covering the fins and the side surfaces of the sidewall spacers. A mask layer is formed on a portion of the first dielectric layer between adjacent gate structures. The mask layer and the protective layer are formed by etching a mask material layer. A second dielectric layer is formed on the first dielectric layer, the protective layer and the sidewall spacers and covering the side surfaces of the mask layer. Conductive vias are formed in the first dielectric layer between the adjacent gate structures and at both sides of the mask layer.Type: GrantFiled: April 20, 2018Date of Patent: September 10, 2019Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Chenglong Zhang, Haiyang Zhang
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Patent number: 10396032Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate; forming an initial metal layer; simultaneously forming a plurality of discrete first metal layers and openings by etching the initial metal layer; forming a plurality of sidewalls covering the side surface of the first metal layers; and forming a plurality of second metal layers to fill the openings.Type: GrantFiled: September 14, 2017Date of Patent: August 27, 2019Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Chenglong Zhang, Haiyang Zhang
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Patent number: 10388761Abstract: A 3-D flash memory device and its manufacturing method, relating to semiconductor technology. The manufacturing method comprises: providing a semiconductor structure comprising a substrate, a first insulation layer on the substrate, a fin structure comprising a first gate layer and a second insulation layer stacked alternately over each other on the first insulation layer, a third insulation layer on two sides of the fin structure, with the first gate layer being surrounded by the first, the second and the third insulation layers, and at least one channel layer covering the fin structure and the third insulation layer; and forming a groove by etching the channel layer, the second insulation layer and the first gate layer along an extension direction of the fin structure. This inventive concept improves the storage density of a 3-D flash memory device.Type: GrantFiled: March 13, 2018Date of Patent: August 20, 2019Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Panpan Liu, Haiyang Zhang
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Patent number: 10388697Abstract: A magnetic random access memory and its manufacturing method related to semiconductor techniques. The magnetic random access memory comprises a word line, a bit line, and a memory unit positioned between the word line and the bit line, wherein the memory unit comprises a fixture layer connecting the bit line, a free layer connecting the word line, and an insulation layer positioned between the fixture layer and the free layer. This magnetic random access memory has a simpler design than conventional devices and can be manufactured more easily, which improves the integrity of the manufacturing process.Type: GrantFiled: October 31, 2017Date of Patent: August 20, 2019Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Zhuofan Chen, Yibin Song, Haiyang Zhang
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Patent number: 10374065Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate, forming a stack of semiconductor layer structures on the first semiconductor layer, and etching the stack to form a fin structure. Each of the semiconductor layer structures includes a first insulator layer and a second semiconductor layer on the first insulator layer. The first and second semiconductor layers have the same semiconductor compound. The fin structure according to the novel method includes one or more insulator layers to achieve a higher on current/off current ratio, thereby improving the device performance relative to conventional fin structures without the insulator layers.Type: GrantFiled: March 29, 2017Date of Patent: August 6, 2019Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Haiyang Zhang, Yan Wang
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Publication number: 20190189511Abstract: A semiconductor device includes a substrate structure comprising an active region, a first interlayer dielectric layer on the active region, and a first opening in the first interlayer dielectric layer and extending to the active region, at least one gate structure in the first opening and comprising spacers on sidewalls of the first opening, a gate dielectric layer on the active region, a metal gate on the gate dielectric layer, and a hardmask on the metal gate and having a first recess in a middle portion of its upper surface, the gate dielectric layer, the metal gate, and the hardmask being between the spacers, a second interlayer dielectric layer on the first dielectric layer and on at least a portion of the hardmask, and a second opening adjacent to the at least one gate structure in the first opening and exposing the spacers and a surface of the active region.Type: ApplicationFiled: February 7, 2019Publication date: June 20, 2019Applicants: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Chenglong Zhang, Erhu Zheng, Haiyang Zhang
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Patent number: 10301687Abstract: A Sidt1 gene controlling a determinate growth habit of sesame, the gene having a length of 1809 bp and including four exons and three introns. The Sidt1 gene is located on the fourth chromosome of sesame and in an 18.0-19.2 cM interval of the eighth linkage group on an SNP genetic map of sesame. The DNA sequence of the Sidt1 gene is represented by SEQ ID NO. 1. A cDNA sequence of the Sidt1 gene has a length of 531 bp and encodes 176 amino acids, and the cDNA sequence is represented by SEQ ID NO. 2. An SNP molecular marker Sidt27-1 of the Sidt1 gene has a length of 92 bp and is located at a base sequence from 378 to 469 of the Sidt1 gene, and a DNA sequence of the SNP molecular marker Sidt27-1 is represented by SEQ ID NO. 3.Type: GrantFiled: April 27, 2017Date of Patent: May 28, 2019Assignee: HENAN SESAME RESEARCH CENTER, HENAN ACADEMY OF AGRICULTURAL SCIENCESInventors: Haiyang Zhang, Hongmei Miao, Chun Li, Libin Wei, Yinghui Duan, Fangfang Xu, Huili Wang
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Patent number: 10242910Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure having an action region and a gate structure having a gate dielectric layer, a gate, a hardmask. The method also includes forming a first dielectric layer on the gate structure, forming a second dielectric layer on the first dielectric layer, performing a surface treatment on the second dielectric layer so that the upper surface of the second dielectric layer is flush with the upper surface of the mask member, which has a first recess is in its middle portion, forming a third dielectric layer on the second dielectric layer covering the mask member and selectively etching the third dielectric layer and the second dielectric layer relative to the first dielectric layer and the hardmask to form an opening adjacent to the gate structure and exposing the first dielectric layer on sidewalls of the gate structure.Type: GrantFiled: June 16, 2017Date of Patent: March 26, 2019Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventors: Chenglong Zhang, Erhu Zheng, Haiyang Zhang
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Patent number: 10134639Abstract: The disclosed subject matter provides a semiconductor structure and fabrication method thereof. In a semiconductor structure, a dielectric layer, a plurality of discrete gate structures, and a plurality of sidewall spacers are formed on a semiconductor substrate. The plurality of discrete gate structures and sidewall spacers are formed in the dielectric layer, and a sidewall spacer is formed on each side of each gate structure. A top portion of each gate structure and a top portion of the dielectric layer between neighboring sidewall spacers of neighboring gate structures are removed. A protective layer is formed on each of the remaining dielectric layer and the remaining gate structures. Contact holes are formed on the semiconductor substrate, between neighboring sidewall spacers, and on opposite sides of the protective layer on the remaining dielectric layer. A metal plug is formed in each contact hole.Type: GrantFiled: September 18, 2017Date of Patent: November 20, 2018Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Chenglong Zhang, Haiyang Zhang
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Publication number: 20180281720Abstract: Provided are a method and device for the rear end collision protection of a vehicle. The method comprises: in a driving process of a current vehicle, detecting a rear vehicle distance by a radar; judging whether the rear vehicle distance is less than a distance threshold, and if yes, calculating a collision time according to the approaching speed of the rear vehicle and the rear vehicle distance; and judging whether the collision time is less than a time threshold, and if yes, initiating an airbag disposed at a rear bumper of the current vehicle, wherein after expanded, the airbag forms a long-strip-shaped inflatable bladder at the outside of the rear bumper of the current vehicle.Type: ApplicationFiled: May 20, 2016Publication date: October 4, 2018Inventors: Xijie ZHAI, Haiyang ZHANG, He ZHU, Dayong ZHOU, Weiguo LIU, Chuanhai LI, Chengming WU, Qingfeng FENG
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Publication number: 20180261687Abstract: A 3-D flash memory device and its manufacturing method, relating to semiconductor technology. The manufacturing method comprises: providing a semiconductor structure comprising a substrate, a first insulation layer on the substrate, a fin structure comprising a first gate layer and a second insulation layer stacked alternately over each other on the first insulation layer, a third insulation layer on two sides of the fin structure, with the first gate layer being surrounded by the first, the second and the third insulation layers, and at least one channel layer covering the fin structure and the third insulation layer; and forming a groove by etching the channel layer, the second insulation layer and the first gate layer along an extension direction of the fin structure. This inventive concept improves the storage density of a 3-D flash memory device.Type: ApplicationFiled: March 13, 2018Publication date: September 13, 2018Inventors: Panpan LIU, Haiyang ZHANG
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Publication number: 20180247867Abstract: A semiconductor structure includes a semiconductor substrate having fins and gate structures on the fins. A protective layer is formed on top surfaces of the gate structures. Sidewall spacers are formed on side surfaces of the gate structures and the protective layer. A first dielectric layer is formed on the surface of the semiconductor substrate and covering the fins and the side surfaces of the sidewall spacers. A mask layer is formed on a portion of the first dielectric layer between adjacent gate structures. The mask layer and the protective layer are formed by etching a mask material layer. A second dielectric layer is formed on the first dielectric layer, the protective layer and the sidewall spacers and covering the side surfaces of the mask layer. Conductive vias are formed in the first dielectric layer between the adjacent gate structures and at both sides of the mask layer.Type: ApplicationFiled: April 20, 2018Publication date: August 30, 2018Inventors: CHENGLONG ZHANG, HAIYANG ZHANG