Abstract: The present disclosure provides a semiconductor structure and a forming method thereof. The forming method includes forming sacrificial layers and spacer on a dielectric layer, wherein the sacrificial layers and the spacer cover the dielectric layer at the top of a gate and expose the dielectric layer on at least part of source-drain doping layers, the sacrificial layers include the first sacrificial layer located on the dielectric layer at the top of the gate, and side walls of the first sacrificial layer are provided with the spacer; after the sacrificial layers and the spacer is formed, the first sacrificial layer is removed; and the dielectric layer is etched with a patterning layer as a mask, and a first contact hole and second contact holes are formed in the dielectric layer. The embodiments and implementations of the present disclosure can avoid double graphics of the dielectric layer and the alignment error.

Abstract: A pipetting device includes a portal frame. The portal frame is arranged with a bearing device for bearing a feed pump, a driving mechanism for driving the bearing device to move up and down, and a liquid suction and injection mechanism for sucking or injecting liquid by the feed pump. The bearing device includes a bearing plate with receiving grooves. The driving mechanism includes a first bracing plate connected to the bearing plate, and the frame is arranged with a first motor. The liquid suction and injection mechanism includes a second bracing plate. The first bracing plate is arranged with a second motor. The first motor and the second motor are connected to a PLC.

Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a target etching layer; sequentially forming an initial mask layer, an anti-reflection layer, and a patterned structure on the target etching layer; performing a first etching process on the anti-reflection layer to remove a surface portion of the anti-reflection layer using the patterned structure as a mask; performing a surface treatment process on the patterned structure; and performing a second etching process on the anti-reflection layer until exposing a surface of the initial mask layer.

Abstract: The present disclosure provides a semiconductor structure and a forming method thereof. The forming method includes forming sacrificial layers and spacer on a dielectric layer, wherein the sacrificial layers and the spacer cover the dielectric layer at the top of a gate and expose the dielectric layer on at least part of source-drain doping layers, the sacrificial layers include the first sacrificial layer located on the dielectric layer at the top of the gate, and side walls of the first sacrificial layer are provided with the spacer; after the sacrificial layers and the spacer is formed, the first sacrificial layer is removed; and the dielectric layer is etched with a patterning layer as a mask, and a first contact hole and second contact holes are formed in the dielectric layer. The embodiments and implementations of the present disclosure can avoid double graphics of the dielectric layer and the alignment error.

Abstract: Semiconductor device fabrication method is provided. The method includes providing a substrate; forming a first semiconductor layer on the substrate; forming a stack of semiconductor layer structures on the first semiconductor layer, each of the semiconductor layer structures comprising a second semiconductor layer and a third semiconductor layer on the second semiconductor layer, the second and third semiconductor layers having at least a common compound element, and the third semiconductor layer and the first semiconductor layer having a same semiconductor compound; performing an etching process to form a fin structure; performing a selective etching process on the second semiconductor layer to form a first air gap between the first semiconductor layer and the third semiconductor layer and a second air gap between each of adjacent third semiconductor layers in the stack of one or more semiconductor layer structures; and filling the first and second air gaps with an insulator layer.

Abstract: Semiconductor structure and fabrication method are provided. The method includes providing a substrate including a first region and a second region; forming a plurality of fins on the first region of the substrate; forming a first isolation structure on the first region and the second region of the substrate; forming a gate structure and a dummy gate structure each across fins and the first isolation structure at the first region; forming an epitaxial layer in each fin on two sides of the gate structure; forming a first opening by etching a portion of each of the first isolation structure and the substrate that are at the second region; filling the first opening with a conductive material layer; removing the dummy gate structure and a portion of the conductive material layer in the first opening to form a power rail; and forming a second isolation structure in a second opening.

Abstract: Semiconductor structure and fabrication method are provided. The method includes providing a substrate including a first region and a second region; forming a plurality of fins on the first region of the substrate; forming an isolation structure on the first region and the second region of the substrate; forming a gate structure across the plurality of fins and on the isolation structure at the first region; etching the isolation structure and the substrate at the second region to form a first opening; filling the first opening with a conductive material layer; and etching the gate structure till exposing the isolation structure to form a second opening in the gate structure and removing a portion of the conductive material layer in the first opening to form a power rail.

Abstract: The present disclosure provides a method for forming a semiconductor structure. The method includes providing a to-be-etched layer; forming a plurality of initial sidewall spacers on the to-be-etched layer; and performing at least one modification treatment process on the plurality of initial sidewall spacers to form a plurality of sidewall spacers. Each of the at least one modification treatment process includes modifying the plurality of initial sidewall spacers to form a transition layer on the top and sidewall surfaces of each initial sidewall spacer of the plurality of initial sidewall spacers, and then removing the transition layer.

Abstract: A semiconductor structure and its fabrication method are provided in the present disclosure. The method includes providing a substrate, forming a plurality of fins on the substrate, and forming an isolation structure layer including a plurality of isolation structures on the substrate, each isolation structure being formed between adjacent fins. The method further includes forming a first opening by etching at least one isolation structure of the plurality of isolation structures and a portion of the substrate, and forming a power rail by filling the first opening with a conductive material, where a top surface of the power rail is lower than a top surface of the plurality of fins.

Abstract: A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a base, the base including a pattern dense region and a pattern isolated region; forming a plurality of separate hard mask layers on the base, where adjacent hard mask layers and the base define an opening, and an opening of the pattern isolated region is wider than an opening of the pattern dense region; forming a trimming layer at least on a side wall of the opening of the pattern isolated region, the trimming layer and the hard mask layer constituting a mask structure layer; and etching, using the mask structure layer as a mask, a portion of the thickness of the base exposed by the opening to form a plurality of target pattern layers protruding from the remaining base. Embodiments and implementations of the present disclosure are advantageous for improving a critical dimension uniformity of a target pattern layer in each region.

Abstract: A semiconductor device includes a substrate and a fin structure. The fin structure includes a first semiconductor layer on the substrate, and a stack of one or more semiconductor layer structures. Each of the semiconductor layer structures includes a first insulator layer and a second semiconductor layer on the first insulator layer, the first and second semiconductor layers having a same semiconductor compound.

Abstract: A method for forming a semiconductor structure includes providing a substrate; forming a gate structure on the substrate, the gate structure extending along a first direction; removing a portion of the gate structure to form a trench in the gate structure, the trench penetrating through the gate structure along a second direction which is different form the first direction; performing a first cleaning treatment process on the trench to remove non-metal residues; and performing a second cleaning treatment process on the trench to remove metal residues.

Abstract: A method of forming a method of forming a semiconductor device includes providing a semiconductor structure, etching back each gate structure of a plurality of gate structures to form an opening, forming a barrier layer over the dielectric layer, forming a sacrificial layer over the barrier layer, planarizing the sacrificial layer till a surface of the sacrificial layer is substantially flat, and using a gas cluster ion beam (GCIB) process to planarize the sacrificial layer and the barrier layer, and to remove the sacrificial layer and to provide a planarized barrier layer. The semiconductor structure includes a semiconductor substrate, a fin, the plurality of gate structures, and a dielectric layer over the semiconductor substrate between adjacent gate structures. A top of the dielectric layer is coplanar with a top of each of the plurality of gate structures.

Abstract: A steam spray head includes a main body and a panel fixedly connected with the main body. The panel is provided with multiple steam orifices, and the main body is provided with a cavity, a cover plate sealing the cavity and provided with a water inlet pipe and a heating element fixed at the bottom of the cavity. The panel is provided with a first chamber communicating with the steam orifices, and an opening of the first chamber is sealed by lateral walls of the main body. One side of the main body provided with the panel is provided with a steam passage communicating the cavity with the first chamber, and multiple steam jet tubes, each end of which extends into the first chamber and presses against a corresponding steam orifice to interface with the latter, and the other end of which communicates with the cavity of the main body.

Abstract: A Sidwf1 gene of Sesamum indicum, including two exons and an intron, is 1638 bp in total, and has a sequence represented by SEQ ID NO: 1. Also provided is a method for determining the internode length type in sesame samples, the method including: 1) extracting a genomic DNA of a sesame sample; 2) synthesizing three primers including SiSNPdwf1 F1, SiSNPdwf1 F2, and SiSNPdwf1 R; amplifying the Sidwf1 gene or an allele SiDWF1 thereof with the genomic DNA of the sesame sample as a template, with a combination of SiSNPdwf1 F1, SiSNPdwf1 F2, and SiSNPdwf1 R a combination of SiSNPdwf1 F1 and SiSNPdwf1 R, or a combination of SiSNPdwf1 F2 and SiSNPdwf1 R, as primers, thereby yielding a PCR product; and performing electrophoresis on the PCR product or sequencing the PCR product, and determining the phenotype of the sesame sample according to an electrophoresis or sequencing result.

Abstract: Disclosed is a bamboo strip shaping method, which includes the following steps: S01: cutting a bamboo tube, and removing inner joints, outer joints and bamboo outer skin; S02: trisecting or quartering the bamboo tube in a longitudinal direction to obtain curved bamboo strips; S03: placing the curved bamboo strips in a bamboo strip shaping device for processing; S04: subjecting the curved bamboo strips to steam treatment and heating softening treatment; S05: pressing and shaping the curved bamboo strips to obtain flattened bamboo strips, and drying for a first time under a maintained pressure; S06: wetting bamboo outer skin surfaces and bamboo inner skin surfaces of the flattened bamboo strips, and drying for a second time; and S07: wetting the bamboo outer skin surfaces and the bamboo inner skin surfaces of the flattened bamboo strips, and drying for a third time.

Abstract: A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a base, the base including a pattern dense region and a pattern isolated region; forming a plurality of separate hard mask layers on the base, where adjacent hard mask layers and the base define an opening, and an opening of the pattern isolated region is wider than an opening of the pattern dense region; forming a trimming layer at least on a side wall of the opening of the pattern isolated region, the trimming layer and the hard mask layer constituting a mask structure layer; and etching, using the mask structure layer as a mask, a portion of the thickness of the base exposed by the opening to form a plurality of target pattern layers protruding from the remaining base. Embodiments and implementations of the present disclosure are advantageous for improving a critical dimension uniformity of a target pattern layer in each region.

Abstract: A semiconductor device includes a substrate structure comprising an active region, a first interlayer dielectric layer on the active region, and a first opening in the first interlayer dielectric layer and extending to the active region, at least one gate structure in the first opening and comprising spacers on sidewalls of the first opening, a gate dielectric layer on the active region, a metal gate on the gate dielectric layer, and a hardmask on the metal gate and having a first recess in a middle portion of its upper surface, the gate dielectric layer, the metal gate, and the hardmask being between the spacers, a second interlayer dielectric layer on the first dielectric layer and on at least a portion of the hardmask, and a second opening adjacent to the at least one gate structure in the first opening and exposing the spacers and a surface of the active region.

Abstract: The present disclosure provides a semiconductor device and a fabrication method. The method includes: providing a substrate having fins and forming an initial gate structure across the fins, which covers a portion of a top surface and sidewall surfaces of the fins, and includes an initial first region and an initial second region on the initial first region. A bottom boundary of the initial second region is higher than the top surface of the fins, and a size of the initial first region is larger than a size of the initial second region. A first etching process is performed on sidewalls of the initial gate structure to form a gate structure, which includes a first region formed by etching the initial first region, and a second region formed by etching the initial second region. A size of the first region is smaller than a size of the second region.

Abstract: A semiconductor structure and a method for forming the same are provided.