Patents by Inventor Haizhou Yin

Haizhou Yin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200335435
    Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.
    Type: Application
    Filed: July 1, 2020
    Publication date: October 22, 2020
    Inventors: Jiehui Shu, Xiaoqiang Zhang, Haizhou Yin, Moosung M. Chae, Jinping Liu, Hui Zang
  • Patent number: 10784195
    Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: September 22, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Xiaoqiang Zhang, Haizhou Yin, Moosung M. Chae, Jinping Liu, Hui Zang
  • Publication number: 20190326209
    Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.
    Type: Application
    Filed: April 23, 2018
    Publication date: October 24, 2019
    Inventors: Jiehui Shu, Xiaoqiang Zhang, Haizhou Yin, Moosung M. Chae, Jinping Liu, Hui Zang
  • Patent number: 10269919
    Abstract: A semiconductor device structure is provided. The semiconductor device includes a semiconductor substrate, a first device, and a second device. Each of the first and second devices includes a gate extending in a first direction, source/drain regions respectively formed on opposite first and second sides of the gate, dielectric spacers formed respectively on outer sidewalls of the gate on the first side and the second side, and conductive spacers serving contacts to the source/drain regions and formed respectively on outer sidewalls of the respective gate spacers. A second direction from the source/drain region on the first side to the source/drain region on the second side crosses the first direction.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: April 23, 2019
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huicai Zhong, Qingqing Liang, Haizhou Yin
  • Patent number: 10096717
    Abstract: The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer on the semiconductor substrate, and a semiconductor layer on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region in the semiconductor layer on both sides of the gate stack; and a channel region in the semiconductor layer and located between the source region and the drain region, wherein the MOSFET further comprises a back gate which is located in the semiconductor substrate and has a first doped region as a lower portion of the back gate and a second doped region as an upper portion of the back gate, and the second doped region of the back gate is self-aligned with the gate stack. The MOSFET can adjust a threshold voltage by changing doping type and doping concentration of the back gate.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: October 9, 2018
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huilong Zhu, Qingqing Liang, Haizhou Yin, Zhijiong Luo
  • Patent number: 10008602
    Abstract: A semiconductor device and a method of manufacturing the same are provided, wherein an example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; forming a sacrificial gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the sacrificial gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; filling the void with a dielectric material; forming a third semiconductor layer on the substrate, to form source/drain regions; and forming a gate stack to replace the sacrificial gate stack.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: June 26, 2018
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huilong Zhu, Miao Xu, Haizhou Yin, Qingqing Liang
  • Patent number: 9853153
    Abstract: The present invention provides a method of manufacturing a fin field effect transistor, comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure from an SOI layer; forming source/drain regions (110) on both sides of the basic fin structure; forming a fin structure between the source/drain regions (110) from a basic fin structure; and forming a gate stack across the fin structure. The method of manufacturing a fin field effect transistor provided in the present invention can integrate a high-k gate dielectric layer, a metal gate, and stressed source/drain regions into the fin field effect transistor to enhance the performance of the semiconductor device.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: December 26, 2017
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huilong Zhu, Zhijiong Luo, Haizhou Yin, Qingqing Liang
  • Publication number: 20170288037
    Abstract: A semiconductor device structure is provided. The semiconductor device includes a semiconductor substrate, a first device, and a second device. Each of the first and second devices includes a gate extending in a first direction, source/drain regions respectively formed on opposite first and second sides of the gate, dielectric spacers formed respectively on outer sidewalls of the gate on the first side and the second side, and conductive spacers serving contacts to the source/drain regions and formed respectively on outer sidewalls of the respective gate spacers. A second direction from the source/drain region on the first side to the source/drain region on the second side crosses the first direction.
    Type: Application
    Filed: June 22, 2017
    Publication date: October 5, 2017
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huicai Zhong, Qingqing Liang, Haizhou Yin
  • Patent number: 9716175
    Abstract: A quasi-nanowire transistor and a method of manufacturing the same are provided, the quasi-nanowire transistor comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure on the SOI layer, the basic fin structure comprising at least one silicon/silicon-germanium stack; forming source/drain regions (110) on both sides of the basic fin structure; forming a quasi-nanowire fin from a basic fin structure and an SOI layer thereunder; and forming a gate stack across the quasi-nanowire fin. The method can effectively control gate length characteristics. A semiconductor structure formed by the above method is also provided.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: July 25, 2017
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huilong Zhu, Qingqing Liang, Haizhou Yin, Zhijiong Luo
  • Patent number: 9711612
    Abstract: A semiconductor device structure and a method for fabricating the same. A method for fabricating semiconductor device structure includes forming gate lines on a semiconductor substrate; forming gate sidewall spacers surrounding the gate lines; forming respective source/drain regions in the semiconductor substrate and on either side of the respective gate lines; forming conductive sidewall spacers surrounding the gate sidewall spacers; and cutting off the gate lines, the gate sidewall spacers and the conductive sidewall spacers at predetermined positions, in which the cut gate lines are electrically isolated gates, and the cut conductive sidewall spacers are electrically isolated lower contacts. The method is applicable to the manufacture of contacts in integrated circuits.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: July 18, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huicai Zhong, Qingqing Liang, Haizhou Yin
  • Patent number: 9691878
    Abstract: Provided is a method for manufacturing a MOSFET, including: forming a shallow trench isolation (STI) in a semiconductor substrate to define an active region for the MOSFET; performing etching with the STI as a mask, to expose a surface of the semiconductor substrate, and to protrude a portion of the STI with respect to the surface of the semiconductor substrate, resulting in a protruding portion; forming a first spacer on sidewalls of the protruding portion; forming a gate stack on the semiconductor substrate; forming a second spacer surrounding the gate stack; forming openings in the semiconductor substrate with the STI, the gate stack, the first spacer and the second spacer as a mask; epitaxially growing a semiconductor layer with a bottom surface and sidewalls of each of the openings as a growth seed layer; and performing ion implantation into the semiconductor layer to form source and drain regions.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: June 27, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Science
    Inventors: Haizhou Yin, Huilong Zhu, Changliang Qin, Huaxiang Yin
  • Patent number: 9691899
    Abstract: A semiconductor structure is provided, comprising a substrate (130), a support structure (131), a base region (100), a gate stack, a spacer (240), and a source/drain region, wherein the gate stack is located above the base region (100), and the base region (100) is supported above the substrate (130) by the support structure (131), wherein the support structure (131) has a sigma-shaped lateral cross-section; an isolation structure (123) is formed below edges on both sides of the base region (100), wherein a portion of the isolation structure (123) is connected to the substrate (130); a cavity (112) is formed between the isolation structure (123) and the support structure (131); and a source/drain region is formed on both sides of the base region (100) and the isolation structure (123). Accordingly, a method for manufacturing the semiconductor structure is also provided.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: June 27, 2017
    Inventors: Huilong Zhu, Haizhou Yin, Zhijiong Luo
  • Patent number: 9653550
    Abstract: A MOSFET structure and a method for manufacturing the same are disclosed. The method comprises: a. providing a substrate (100); b. forming a silicon germanium channel layer (101), a dummy gate structure (200) and a sacrificial spacer (102); c. removing the silicon germanium channel layer and portions of the substrate which are not covered by the dummy gate structure (200) and located under both sides of the dummy gate structure 200, so as to form vacancies (201); d. selectively epitaxially growing a first semiconductor layer (300) on the semiconductor structure to fill bottom and sidewalls of the vacancies (201); and e. removing the sacrificial spacer (102) and filling a second semiconductor layer (400) in the vacancies which are not filled by the first semiconductor layer (300). In the semiconductor structure of the present disclosure, carrier mobility in the channel can be increased, negative effects induced by the short channel effects can be suppressed, and device performance can be enhanced.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: May 16, 2017
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Haizhou Yin
  • Patent number: 9640660
    Abstract: A method of fabricating an asymmetric FinFET is provided in the invention, comprising: a. providing a substrate (101); b. forming a fin (102) on the substrate (101), wherein the width of the fin (102) is defined as a second channel thickness; c. forming a shallow trench isolation; d. forming a sacrificial gate stack on the top surface and sidewalls of the channel which is in the middle of the fin, and forming source/drain regions in both ends of the fin; e. depositing an interlayer dielectric layer to cover the sacrificial gate stack and the source/drain regions, planarizing the interlayer dielectric layer to expose sacrificial gate stack; f. removing the sacrificial gate stack to expose the channel; g. forming an etch-stop layer (106) on top of the channel; h. covering a photoresist film (400) on a portion of the semiconductor structure near the source region; i.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: May 2, 2017
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Haizhou Yin, Keke Zhang
  • Patent number: 9614050
    Abstract: The present invention provides a method for manufacturing a semiconductor device, comprising: forming a contact sacrificial pattern on a substrate to cover source and drain regions and expose a gate region; forming an interlayer dielectric layer on the substrate to cover the contact sacrificial pattern and expose the gate region; forming a gate stack structure in the exposed gate region; removing the contact sacrificial pattern to form the source/drain contact trench; and forming a source/drain contact in the source/drain contact trench. By means of a contact sacrificial layer process, the method of manufacturing a semiconductor device according to the present invention effectively reduces the distance between the gate spacer and the contact region and increases the area of the contact region, thus effectively reducing the parasitic resistance of the device.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: April 4, 2017
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Haizhou Yin, Keke Zhang
  • Patent number: 9608064
    Abstract: Provided is a MOSFET, comprising: a substrate (100); a gate stack (500) on the substrate (100); source/drain regions (305) in the substrate on both sides of the gate stack (500); an interlayer dielectric layer (400) covering the source/drain regions; and source/drain extension regions (205) under edges on both sides of the gate stack (500); wherein insulators, which are not connected each other, are formed beneath the source/drain extension regions (205) under edges on both sides of the gate stack (500). By means of the MOSFET in the present disclosure, negative effects induced by DIBL on device performance can be effectively reduced.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: March 28, 2017
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Haizhou Yin, Rui Li
  • Patent number: 9583622
    Abstract: The present invention discloses a semiconductor structure and a method for manufacturing the same, which comprises providing a substrate, and forming a stress layer, a buried oxide layer, and an SOI layer on the substrate; forming a doped region of the stress layer arranged in a specific position in the stress layer; forming an oxide layer and a nitride layer on the SOI layer, and forming a first trench that etches the nitride layer, the oxide layer, the SOI layer, and the buried oxide layer, and stops on the upper surface of the stress layer, and exposes at least part of the doped region of the stress layer; forming a cavity by wet etching through the first trench to remove the doped region of the stress layer; forming a polycrystalline silicon region of the stress layer and a second trench by filling the cavity with polycrystalline silicon and etching back; forming an isolation region by filling the second trench.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: February 28, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhijiong Luo, Haizhou Yin, Qingqing Liang
  • Patent number: 9576802
    Abstract: A method for manufacturing a semiconductor device is disclosed. The method comprises: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; forming a T-shape metal gate structure by filling a metal layer in the T-shape gate trench. According to the semiconductor device manufacturing method disclosed in the present application, the overhang phenomenon and the formation of voids are avoided in the subsequent metal gate filling process by forming a T-shape dummy gate and a T-shape gate trench, and the device performance is improved.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: February 21, 2017
    Inventors: Haizhou Yin, Huilong Zhu, Keke Zhang
  • Patent number: 9577074
    Abstract: A method of manufacturing a FinFET device is provided, comprising: a. providing a substrate (100); b. forming a fin (200) on the substrate; c. forming an shallow trench isolation structure (300) on the substrate; d. forming an sacrificial gate stack on the isolation structure, wherein the sacrificial gate stack intersects the fin; e. forming source/drain doping regions by ion implantation into the fin; f. depositing an interlayer dielectric layer (400) on the substrate; g. removing the sacrificial gate stack to form a sacrificial gate vacancy; h. forming an doped region (201) under the sacrificial gate vacancy; i. etching the shallow trench isolation structure (300) under the sacrificial gate vacancy until the top surface of the shallow trench isolation structure (300) levels with the bottom surface of the source/drain doping regions; j. forming a new gate stack in the sacrificial gate vacancy.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: February 21, 2017
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Yunfei Liu, Haizhou Yin, Keke Zhang
  • Patent number: 9548317
    Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises following steps: providing a substrate, which comprises upwards in order a base layer, a buried isolation layer, a buried ground layer, an ultra-thin insulating buried layer and a surface active layer; implementing ion implantation doping to the buried ground layer; forming a gate stack, sidewall spacers and source/drain regions on the substrate; forming a mask layer on the substrate that covers the gate stack and the source/drain regions, and etching the mask layer to expose the source region; etching the source region and the ultra-thin insulating buried layer under the source region to form an opening that exposes the buried ground layer; filling the opening through epitaxial process to form a contact plug for the buried ground layer. Accordingly, the present invention further provides a semiconductor structure.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: January 17, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo