Abstract: A semiconductor device and a method of manufacturing the same are provided, wherein an example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; forming a sacrificial gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the sacrificial gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; filling the void with a dielectric material; forming a third semiconductor layer on the substrate, to form source/drain regions; and forming a gate stack to replace the sacrificial gate stack.

Abstract: A method for manufacturing a semiconductor structure is disclosed. The method comprises: providing an SOI substrate (200) comprising, from bottom to top, a base layer (201), a buried insulator layer (202), and a surface active layer (203); forming a gate stack on the substrate; removing the surface active layer (203) on both sides of the gate stack and removing a part of the buried insulator layer (202) to form an opening (240); filling the opening (240) with semiconductor materials so as to form source/drain regions (250). Correspondingly, a semiconductor structure is also disclosed. In the present disclosure, by extending the source/drain region to the buried insulator layer of the substrate, the source/drain series resistance is reduced while not increasing parasitic capacitance between the gate and the source/drain regions.

Abstract: The present invention provides a method of manufacturing a fin field effect transistor, comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure from an SOI layer; forming source/drain regions (110) on both sides of the basic fin structure; forming a fin structure between the source/drain regions (110) from a basic fin structure; and forming a gate stack across the fin structure. The method of manufacturing a fin field effect transistor provided in the present invention can integrate a high-k gate dielectric layer, a metal gate, and stressed source/drain regions into the fin field effect transistor to enhance the performance of the semiconductor device.

Abstract: A semiconductor structure is disclosed. The semiconductor structure comprises: a substrate (130), a support structure (131), a base region (100), a gate stack, a spacer (240), and a source/drain region, wherein the gate stack is located on the base region (100), and the base region (100) is supported on the substrate (130) by the support structure (131), wherein the sidewall cross-section of the support structure (131) is in a shape of a concave curve; an isolation structure (123) is formed beneath the edges on both sides of the base region (100), wherein a portion of the isolation structure (123) is connected to the substrate (130); a cavity (112) is formed between the isolation structure (123) and the support structure (131); and there exists a source/drain region at least on both sides of the base region (100) and the isolation structure (123). Accordingly, a method for manufacturing the semiconductor structure is also disclosed.

Abstract: A semiconductor device and a method for manufacturing the same are provided. In one embodiment, the method comprises: growing a first epitaxial layer on a substrate; forming a sacrificial gate stack on the first epitaxial layer; selectively etching the first epitaxial layer; growing and in-situ doping a second epitaxial layer on the substrate; forming a spacer on opposite sides of the sacrificial gate stack; and forming source/drain regions with the spacer as a mask.

Abstract: The present invention provides a method of manufacturing a fin structure of a FinFET, comprising: providing a substrate (200); forming a first dielectric layer (210); forming a second dielectric layer (220), the material of the portion where the second dielectric layer is adjacent to the first dielectric layer being different from that of the first dielectric layer (210); forming an opening (230) through the second dielectric layer (220) and the first dielectric layer (2100, the opening portion exposing the substrate; filling a semiconductor material in the opening (230); and removing the second dielectric layer (220) to form a fin structure. In the present invention, the height of the fin structure in the FinFET is controlled by the thickness of the dielectric layer. The etching stop can be controlled well by using the etching selectivity between different materials, which can achieve etching uniformity better compared to time control.

Abstract: A method for manufacturing a semiconductor structure is disclosed. The method comprises: providing an SOI substrate, which comprises, from top to bottom, an SOI layer (100), a BOX layer (110) and a base layer (130); forming a dummy gate stack on the SOI substrate and an implantation barrier layer on both sides of the dummy gate stack; removing the dummy gate stack to form a gate recess (220); and performing, via the gate recess (220), implantation of stress inducing ions to the semiconductor structure and annealing to form, right below the gate recess (220), a stress inducing region (150) under the BOX layer (110) of the SOI substrate. Accordingly, the present invention further provides a semiconductor structure manufactured according to the above method.

Abstract: A method for manufacturing a semiconductor structure is disclosed. The method comprises: a) providing an SOI substrate, and forming a gate stack on the SOI substrate; b) conducting amorphous implantation to source/drain regions, wherein process temperature of the amorphous implantation to the source region is higher than process temperature of the amorphous implantation to the drain region; c)performing the source/drain region doping; d) annealing to activate the impurities and recrystallize the amorphous region of the source/drain regions. In step b), the process temperature is higher than 50 in the amorphous implantation to the source region whereas the process temperature is lower than ?30 in the amorphous implantation to the drain region. The present invention provides a method to generate defects under the source region. The defects can serve as discharge channels for the charges accumulated in the bulk region to reduce the impact of the floating bulk effect and to improve the reliability of the device.

Abstract: Provided are semiconductor devices and methods for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second semiconductor layer and the first semiconductor layer to form a fin; forming an isolation layer on the substrate, wherein the isolation layer exposes a portion of the first semiconductor layer; implanting ions into a portion of the substrate beneath the fin, to form a punch-through stopper; forming a gate stack crossing over the fin on the isolation layer; selectively etching the second semiconductor layer with the gate stack as a mask, to expose the first semiconductor layer; selectively etching the first semiconductor layer, to form a void beneath the second semiconductor layer; and forming a third semiconductor layer on the substrate, to form source/drain regions.

Abstract: A method for manufacturing a MOSFET, including: performing ion implantation, via a shallow trench surrounding an active region in a semiconductor substrate, into a first sidewall of the active region and into a second sidewall of the active region opposite to the first sidewall to form a first heavily doped region in the first sidewall and a second heavily doped region in the second sidewall; filling the shallow trench with an insulating material, to form a shallow trench isolation; forming a gate stack and an insulating layer on the substrate, wherein the insulating layer surrounds and caps the gate stack; forming openings in the substrate using the shallow trench isolation, the first and second heavily doped regions, and the insulating layer as a hard mask; and epitaxially growing a semiconductor layer with a bottom surface and sidewalls of each of the openings as a seed layer.

Abstract: A quasi-nanowire transistor and a method of manufacturing the same are provided, the quasi-nanowire transistor comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure on the SOI layer, the basic fin structure comprising at least one silicon/silicon-germanium stack; forming source/drain regions (110) on both sides of the basic fin structure; forming a quasi-nanowire fin from a basic fin structure and an SOI layer thereunder; and forming a gate stack across the quasi-nanowire fin. The method can effectively control gate length characteristics. A semiconductor structure formed by the above method is also provided.

Abstract: The present invention discloses a method for manufacturing a semiconductor structure, which comprises the following steps: a) providing an SOI substrate, a shallow trench is formed on the SOI substrate, with the defined area of the shallow trench corresponding to the active region; b) forming the heavily doped layer on the shallow trench sidewall close to the active region; c) filling the shallow trench to form the shallow trench isolation structure; d) forming the semiconductor device in the active region. In the present disclosure, PN junctions are formed in the source electrode and the body region of the SOI, to provide a discharge channel for the charge accumulated in the body region, to reduce the impact of the floating body effect, and to improve the reliability of the device.

Abstract: A method for manufacturing a semiconductor device is disclosed. The method comprises forming a etch stop layer and a dummy gate layer on a substrate; forming a dummy gate pattern by wet etching the dummy gate layer; forming a gate spacer around said dummy gate pattern; removing said dummy gate pattern by wet etching to form a gate trench; and forming a gate stack in the gate trench. In the method for manufacturing a semiconductor device according to the invention, epitaxial monocrystalline thin film is used as the dummy gate and the stop layer for wet etching the dummy gate. As a result, the verticality of the gate profile is improved, erosion of substrate at corner of the bottom is avoided, and therefore performance and reliability of the device is effectively improved.

Abstract: The present invention provides a method for manufacturing a shallow trench isolation, comprising: forming a hard mask layer on the substrate; phottoetching/etching the hard mask layer and the substrate to form a plurality of first trenches along a first direction and a plurality of second trenches along a second direction perpendicular to the first direction, wherein the volume of the second trench is greater than that of the first trench; depositing an insulating material in the first and second trenches; planarizing the insulating material and the hard mask layer until the substrate is exposed so as to form a shallow trench isolation.

Abstract: A MOSFET with a graphene nano-ribbon, and a method for manufacturing the same are provided. The MOSFET comprises an insulating substrate; and an oxide protection layer on the insulating substrate. At least one graphene nano-ribbon is embedded in the oxide protection layer and has a surface which is exposed at a side surface of the oxide protection layer. A channel region is provided in each of the at least one graphene nano-ribbon. A source region and a drain regions are provided in each of the at least one graphene nano-ribbon. The channel region is located between the source region and the drain region. A gate dielectric is positioned on the at least one graphene nano-ribbon. A gate conductor on the gate dielectric. A source and drain contacts contact the source region and the drain region respectively on the side surface of the oxide protection layer.

Abstract: A FinFET with reduced leakage between source and drain regions, and a method for manufacturing the FinFET are disclosed. In one aspect, the method includes forming, on a semiconductor substrate, at least two openings to define a semiconductor fin. The method also includes forming a gate dielectric layer that conformally covers the fin and the openings. The method also includes forming, within the openings, a first gate conductor adjacent to the bottom of the fin. The method also includes forming, within the openings, an insulating isolation layer on the first gate conductor. The method also includes forming a second gate conductor on the fin and on the insulating isolation layer adjacent to the top of the fin. The method also includes forming spacers on sidewalls of the second gate conductor. The method also includes forming a source region and a drain region in the fin.

Abstract: The present invention provides a method for manufacturing a semiconductor device, comprising: forming a contact sacrificial pattern on a substrate to cover source and drain regions and expose a gate region; forming an interlayer dielectric layer on the substrate to cover the contact sacrificial pattern and expose the gate region; forming a gate stack structure in the exposed gate region; removing the contact sacrificial pattern to form the source/drain contact trench; and forming a source/drain contact in the source/drain contact trench. By means of a contact sacrificial layer process, the method of manufacturing a semiconductor device according to the present invention effectively reduces the distance between the gate spacer and the contact region and increases the area of the contact region, thus effectively reducing the parasitic resistance of the device.

Abstract: An isolation region is provided. The isolation region includes a first groove and an insulation layer filling the first groove. The first groove is embedded into a semiconductor substrate and includes a first sidewall, a bottom surface and a second sidewall that extends from the bottom surface and joins to the first sidewall. An angle between the first sidewall and a normal line of the semiconductor substrate is larger than a standard value. A method for forming an isolation region is further provided. The method includes: forming a first trench on a semiconductor substrate, wherein an angle between a sidewall of the first trench and a normal line of the semiconductor substrate is larger than a standard value; forming a mask on the sidewall to form a second trench on the semiconductor substrate by using the mask; and forming an insulation layer to fill the first and second trenches. A semiconductor device and a method for forming the same are still further provided.

Abstract: The present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: providing a semiconductor substrate, forming an insulating layer on the semiconductor substrate, and forming a semiconductor base layer on the insulating layer; forming a sacrificial layer and a spacer surrounding the sacrificial layer on the semiconductor base layer, and etching the semiconductor base layer by taking the spacer as a mask to form a semiconductor body; forming a dielectric film on sidewalls of the semiconductor body; removing the sacrificial layer and the semiconductor body located under the sacrificial layer to form a first semiconductor fin and a second semiconductor fin; and forming a retrograde doped well structure on the inner walls of the first semiconductor fin and the second semiconductor fin, wherein the inner walls thereof are opposite to each other. Correspondingly, the present invention further provides a semiconductor structure.

Abstract: A method for manufacturing a semiconductor device, comprising: forming a gate stack structure and gate spacers on the substrate; forming the raised S/D regions on the substrate on both sides of the gate stack structure and the gate spacers; depositing a lower interlayer dielectric layer on the entire device, and planarizing the lower interlayer dielectric layer and the gate stack structure until the raised S/D regions are exposed; selective epitaxial growing to form the S/D extension regions in the raised S/D regions; forming an upper interlayer dielectric layer on the S/D extension regions; etching the upper interlayer dielectric layer until the S/D extension regions to form an S/D contact hole; forming a metal silicide in the S/D contact hole.