Abstract: A well region formation method and a semiconductor base in the field of semiconductor technology are provided. A method comprises: forming isolation regions in a semiconductor substrate to isolate active regions; selecting at least one of the active regions, and forming a first well region in the selected active region; forming a mask to cover the selected active region, and etching the rest of the active regions, so as to form grooves; and growing a semiconductor material by epitaxy to fill the grooves. Another method comprises: forming isolation regions in a semiconductor substrate for isolating active regions; forming well regions in the active regions; etching the active regions to form grooves, such that the grooves have a depth less than or equal to a depth of the well regions; and growing a semiconductor material by epitaxy to fill the grooves.

Abstract: A method of manufacturing a semiconductor structure, which comprises the steps of: providing a substrate, forming a fin on the substrate, which comprises a central portion for forming a channel and an end portion for forming a source/drain region and a source/drain extension region; forming a gate stack to cover the central portion of the fin; performing light doping to form a source/drain extension region in the end portion of the fin; forming a spacer on sidewalls of the gate stack; performing heavy doping to form a source/drain region in the end portion of the fin; removing at least a part of the spacer to expose at least a part of the source/drain extension region; forming a contact layer on an upper surface of the source/drain region and an exposed area of the source/drain extension region. Correspondingly, the present invention also provides a semiconductor structure.

Abstract: The present invention relates to enhancing MOSFET performance with the corner stresses of STI.

Abstract: The invention provides a semiconductor device comprising: a substrate; a gate, which is formed on the substrate; a source and a drain, which are located on opposite sides of the gate, respectively; a contact, which contacts with the source and/or the drain, wherein the contact has an enlarged end at an end which is in contact with the source and/or the drain. In the present invention, since the contact area of the contact is increased on the interface in contact with the source/the drain, the contact resistance can be reduced, and thus the performances of the semiconductor device can be guaranteed/improved. The present invention further provides a method of fabricating the semiconductor device (especially the contact therein) as previously described.

Abstract: The present invention provides a semiconductor structure comprising a substrate, a gate stack, a sidewall, a base region, source/drain regions, and a support structure, wherein: the base region is located above the substrate, and is separated from the substrate by the void; said support structure is located on both sides of the void, in which part of the support isolation structure is connected with the substrate; the gate stack is located above the base region, said sidewall surrounding the gate stack; said source/drain regions are located on both sides of the gate stack, the base region and the support isolation structure, in which the stress in the source/drain regions first gradually increases and then gradually decreases along the height direction from the bottom. The present invention also provides a manufacturing method for the semiconductor structure. The present invention is beneficial to suppress the short channel effect, as well as to provide an optimum stress to the channel.

Abstract: The present invention provides a method for manufacturing a semiconductor structure. The method comprises: providing an SOI substrate and forming a gate structure on said SOI substrate; etching a SOI layer and a BOX layer of the SOI substrate on both sides of the gate structure to form a trench exposing the BOX layer, said trench partially entering into the BOX layer; forming a stressed layer that fills up a part of said trench; forming a semiconductor layer covering the stressed layer in the trench. Correspondingly, the present invention also provides a semiconductor structure formed by the above method. In the semiconductor structure and the method for manufacturing the same according to the present invention, a trench is formed on an ultrathin SOI substrate, first filled with a stressed layer, and then filled with a semiconductor material to be ready for forming a source/drain region.

Abstract: The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along <110> crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.

Abstract: There is provided a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention comprises: a semiconductor substrate; a channel region formed on the semiconductor substrate; a gate stack formed on the channel region; and source/drain regions formed on both sides of the channel region and embedded in the semiconductor substrate. The gate stack comprises: a gate dielectric layer formed on the channel region; and a conductive layer positioned on the gate dielectric layer. For an nMOSFET, the conductive layer has a compressive stress to apply a tensile stress to the channel region; and for a pMOSFET, the conductive layer has a tensile stress to apply a compressive stress to the channel region.

Abstract: A method for forming a field effect device includes forming a gate portion on a silicon-on-insulator layer (SOI), forming first spacer members on the SOI layer adjacent to the gate portion, depositing a layer of spacer material on the SOI layer, the first spacer members, and the gate portion, removing portions of the layer of spacer material to form second spacer members on the SOI layer adjacent to the first spacer members, forming a source region and a drain region on the SOI layer by implanting ions in the SOI layer, and etching to remove the second spacer members.

Abstract: The present invention provides a semiconductor structure, which comprises: a substrate, a semiconductor base, a semiconductor auxiliary base layer, a cavity, a gate stack, a sidewall spacer, and a source/drain region, wherein the gate stack is located on the semiconductor base; the sidewall spacer is located on the sidewalls of the gate stack; the source/drain region is embedded in the semiconductor base and is located on both sides of the gate stack; the cavity is embedded in the substrate; the semiconductor base is suspended above the cavity, the thickness of the middle portion of the semiconductor base is greater than the thickness of the two end portions of the semiconductor base in the direction of the length of the gate, and the two end portions of the semiconductor base are connected to the substrate in the direction of the width of the gate; and the semiconductor auxiliary base layer is located on the sidewall of the semiconductor base and has an opposite doping type to that of the source/drain region

Abstract: The present invention provides a strip plate structure and a method for manufacturing the same. The strip plate structure comprises a strip plate array, which comprises a plurality of strip plates arranged with spacing in a predetermined direction on a same plane, wherein each of the strip plates has a first surface and a second surface opposite to the first surface and the strip plate array is arranged on a plane parallel to the first surface of the strip plates; a plurality of strip sheets which connect neighboring ones of the strip plates; flexible material layers, which are located on at least a portion of the surfaces of the strip sheets and/or on at least a portion of the surfaces of the strip plates.

Abstract: A strip plate structure and a method of manufacturing the same are disclosed. In one embodiment, the strip plate structure comprises a strip plate array comprising a plurality of strip plates arranged in a predetermined direction with spacing. Each of the strip plates includes a first surface facing one side direction of the strip plate structure and a second surface facing an substantially opposite side direction of the strip plate structure; and a plurality of strip sheets. Each strip sheet alternately abuts either the first surfaces or the second surfaces of two adjacent strip plates.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises: a semiconductor layer comprising a plurality of semiconductor sub-layers; and a plurality of fins formed in the semiconductor layer and adjoining the semiconductor layer, wherein at least two of the plurality of fins comprise different numbers of the semiconductor sub-layers and have different heights. According to the present disclosure, a plurality of semiconductor devices with different dimensions and different driving abilities can be integrated on a single wafer.

Abstract: Semiconductor devices and methods for manufacturing the semiconductor devices are disclosed. A semiconductor device includes a substrate, a fin formed above the substrate with a semiconductor layer formed between the substrate and the fin, and a gate stack crossing over the fin. The fin and the semiconductor layer may include different materials and have etching selectivity with respect to each other. A patterning of the fin can be stopped reliably on the semiconductor layer. Therefore, it is possible to better control the height of the fin and thus the channel width of the final device.

Abstract: A semiconductor structure and a method for manufacturing the same are disclosed. The method comprises: disposing a first dielectric material layer on a first semiconductor layer and defining openings in the first dielectric material layer; epitaxially growing a second semiconductor layer on the first semiconductor layer via the openings defined in the first dielectric material layer, wherein the second semiconductor layer and the first semiconductor layer comprise different materials from each other; and forming plugs of a second dielectric material in the second semiconductor layer at positions where the openings are defined in the first dielectric material layer and also at middle positions between adjacent openings. According to embodiments of the disclosure, defects occurring during the heteroepitaxial growth can be effectively suppressed.

Abstract: A method for making FinFETs and semiconductor structures formed therefrom is disclosed, comprising: providing a SiGe layer on a Si semiconductor substrate and a Si layer on the SiGe layer, wherein the lattice constant of the SiGe layer matches that of the substrate; patterning the Si layer and the SiGe layer to form a Fin structure; forming a gate stack on top and both sides of the Fin structure and a spacer surrounding the gate stack; removing a portion of the Si layer which is outside the spacer with the spacer as a mask, while keeping a portion of the Si layer which is inside the spacer; removing a portion of the SiGe layer which is kept after the patterning, to form a void; forming an insulator in the void; and epitaxially growing stressed source and drain regions on both sides of the Fin structure and the insulator.

Abstract: It is provided a method for forming a semiconductor device comprising: forming a material layer which exposes dummy gates and sidewall spacers and fills spaces between two adjacent gate stacks, and the material of the material layer is the same as the material of the dummy gate; removing the dummy gates and the material layer to form recesses; filling the recesses with a conductive material, and planarizing the conductive material to expose the sidewall spacers; breaking the conductive material outside the sidewall spacers to form at least two conductors, each of the conductors being only in contact with the active region at one side outside one of the sidewall spacers, so as to form gate stack structures and first contacts. Besides, a semiconductor device is provided. The method and the semiconductor device are favorable for extending process windows in forming contacts.

Abstract: The present invention provides a method for manufacturing a semiconductor structure, which comprises: providing an SOI substrate, forming a gate structure on the SOI substrate; etching an SOI layer of the SOI substrate and a BOX layer of the SOI substrate on both sides of the gate structure to form trenches, the trenches exposing the BOX layer and extending partly into the BOX layer; forming sidewall spacers on sidewalls of the trenches; forming inside the trenches a metal layer covering the sidewall spacers, wherein the metal layer is in contact with the SOI layer which is under the gate structure. Accordingly, the present invention further provides a semiconductor structure formed according to aforesaid method.

Abstract: Semiconductor structure and methods for manufacturing the same are disclosed.

Abstract: The present application discloses a semiconductor device comprising a fin of semiconductive material formed from a semiconductor layer over a semiconductor substrate and having two opposing sides perpendicular to the main surface of the semiconductor substrate; a source region and a drain region provided in the semiconductor substrate adjacent to two ends of the fin and being bridged by the fin; a channel region provided at the central portion of the fin; and a stack of gate dielectric and gate conductor provided at one side of the fin, where the gate conductor is isolated from the channel region by the gate dielectric, and wherein the stack of gate dielectric and gate conductor extends away from the one side of the fin in a direction parallel to the main surface of the semiconductor substrate, and insulated from the semiconductor substrate by an insulating layer.