Abstract: There is provided an aluminum nitride laminate member including: a sapphire substrate having a base surface on which bumps are distributed periodically, each bump having a height of smaller than or equal to 500 nm; and an aluminum nitride layer grown on the base surface and having a flat surface, there being substantially no voids in the aluminum nitride layer.

Abstract: There is provided an aluminum nitride laminate member including: a sapphire substrate having a base surface on which bumps are distributed periodically, each bump having a height of smaller than or equal to 500 nm; and an aluminum nitride layer provided on the base surface and having a surface on which protrusions are formed above the apices of the bumps.

Abstract: A nitride semiconductor laminate includes: a substrate comprising a group III nitride semiconductor and including a surface and a reverse surface, the surface being formed from a nitrogen-polar surface, the reverse surface being formed from a group III element-polar surface and being provided on the reverse side from the surface; a protective layer provided at least on the reverse surface side of the substrate and having higher heat resistance than the reverse surface of the substrate; and a semiconductor layer provided on the surface side of the substrate and comprising a group III nitride semiconductor. The concentration of O in the semiconductor layer is lower than 1×1017 at/cm3.

Abstract: To provide a new GaN laminate obtained b growing a GaN layer on a GaN substrate by HVPE, including: a GaN substrate containing GaN single crystal and having a low index crystal plane as c-plane closest to a main surface; and a GaN layer epitaxially grown on the main surface of the GaN substrate wherein a surface of the GaN layer has a macro step-macro terrace structure in which a macro step and a macro terrace are alternately arranged, one of the macro step and the macro terrace has a step-terrace structure in which a step having a height of equal to or more than a plurality of molecular layers of GaN and extending in a direction orthogonal to m-axis direction, and a terrace are alternately arranged, and the other one of the macro step and the macro terrace has a step-terrace structure in which a step having a height of equal to or more than a plurality of molecular layers of GaN and extending in a direction orthogonal to a-axis direction, and a terrace are alternately arranged.

Abstract: There is provided a nitride semiconductor template, including: a substrate having a front surface and a back surface opposite to the front surface; a back side semiconductor layer provided on a back surface side of the substrate, comprising a polycrystalline group III nitride semiconductor, and having a linear expansion coefficient different from a linear expansion coefficient of the substrate; and a front side semiconductor layer provided on a front surface side of the substrate, comprising a monocrystalline group III nitride semiconductor, and having a linear expansion coefficient different from a linear expansion coefficient of the substrate, wherein a thickness of the front side semiconductor layer is a thickness exceeding a critical thickness at which cracks are generated in the front side semiconductor layer when only the front side semiconductor layer is formed without forming the back side semiconductor layer.

Abstract: An object of the present invention is to improve quality of a nitride crystal, and also improve performance and manufacturing yield of a semiconductor device manufactured using the crystal. Provided is a nitride crystal in which a composition formula is represented by InxAlyGa1-x-yN (satisfying 0?x?1, 0?y?1, 0?x+y?1), and the concentration of B in the crystal is less than 1×1015 at/cm3, and each of the concentrations of O and C in the crystal is less than 1×1015 at/cm3 in a region of 60% or more of a main surface.

Abstract: An object of the present invention is to improve quality of a group-III nitride crystal, and also improve performance and manufacturing yield of a semiconductor device manufactured using the crystal. Provided is a nitride crystal represented by the composition formula of InxAlyGa1-x-yN (satisfying 0?x?1, 0?y?1, 0?x+y?1), with a hardness exceeding 22.0 GPa as measured by a nanoindentation method using an indenter with a maximum load applied thereto being within a range of 1 mN or more and 50 mN or less.

Abstract: A nitride semiconductor template includes a heterogeneous substrate, a first nitride semiconductor layer that is formed on one surface of the heterogeneous substrate, includes a nitride semiconductor and has an in-plane thickness variation of not more than 4.0%, and a second nitride semiconductor layer that is formed on an annular region including an outer periphery of an other surface of the heterogeneous substrate, includes the nitride semiconductor and has a thickness of not less than 1 ?m.

Abstract: Provided is a semi-insulating crystal represented by a composition formula InxAlyGa1-x-yN (satisfying 0?x?1, 0?y?1, 0?x+y?1), wherein each concentration of Si, B, and Fe in the crystal is less than 1×1015 at/cm3, electric resistivity under a temperature condition of 20° C. or more and 200° C. or less is 1×106 ?cm or more.

Abstract: A nitride semiconductor template includes a substrate, and a chlorine-containing nitride semiconductor layer. The chlorine-containing nitride semiconductor layer contains an iron concentration of not higher than 1×1017 cm?3.

Abstract: To provide a new GaN laminate obtained by growing a GaN layer on a GaN substrate by HVPE, including: a GaN substrate containing GaN single crystal and having a low index crystal plane as c-plane closest to a main surface; and a GaN layer epitaxially grown on the main surface of the GaN substrate, and having a thickness of 10 nm or more, wherein a surface of the GaN layer has a step-terrace structure in which a step having a height of equal to or more than a plurality of molecular layers of GaN and extending in a predetermined direction and a terrace are alternately arranged.

Abstract: To provide a new GaN laminate obtained b growing a GaN layer on a GaN substrate by HVPE, including: a GaN substrate containing GaN single crystal and having a low index crystal plane as c-plane closest to a main surface; and a GaN layer epitaxially grown on the main surface of the GaN substrate wherein a surface of the GaN layer has a macro step-macro terrace structure in which a macro step and a macro terrace are alternately arranged, one of the macro step and the macro terrace has a step-terrace structure in which a step having a height of equal to or more than a plurality of molecular layers of GaN and extending in a direction orthogonal to m-axis direction, and a terrace are alternately arranged, and the other one of the macro step and the macro terrace has a step-terrace structure in which a step having a height of equal to or more than a plurality of molecular layers of GaN and extending in a direction orthogonal to a-axis direction, and a terrace are alternately arranged.

Abstract: To provide a technique of increasing a radius of curvature of (0001) plane, and narrowing an off-angle distribution, there is provided a nitride semiconductor substrate containing a group III nitride semiconductor crystal and having a main surface in which a nearest low index crystal plane is (0001) plane, wherein (0001) plane in one of a direction along <1-100> axis and a direction along <11-20> axis orthogonal to the <1-100> axis, is curved in a concave spherical shape with respect to the main surface, and a radius of curvature of the (0001) plane in one of the direction along the <1-100> axis and the direction along the <11-20> axis orthogonal to the <1-100> axis is different from a radius of curvature of at least a part of the (0001) plane in the other direction.

Abstract: There is provided a substrate processing apparatus, comprising: a substrate placing table which is provided to at least one of the temperature elevating part and the temperature lowering part formed in a container, and which causes heat-transfer to occur with the substrate placed on a placing surface; and a temperature control part which controls a temperature of the substrate placing table, wherein the temperature control part is configured to: control the temperature of the substrate placing table so that the temperature of the substrate to be loaded into the processing part is elevated to a predetermined temperature, before the substrate is placed on the substrate placing table, when the substrate placing table is provided to the temperature elevating part; and control the temperature of the substrate placing table so that the temperature of the processed substrate unloaded from the processing part is lowered to a predetermined temperature, before the substrate is placed on the substrate placing table, whe

Abstract: A wafer inspection apparatus including a light emitter configured to emit light onto a to-be-inspected surface of a wafer, an imaging unit configured to obtain an image formed by the light emitted from the light emitter and reflected by the to-be-inspected surface, a moving unit configured to move a to-be-inspected position on the to-be-inspected surface by controlling a position of one of the wafer and the light emitter, and an inspecting unit configured to inspect the to-be-inspected surface by detecting a scatter image formed by the light that is emitted from the light emitter and scattered by a defect of the to-be-inspected surface, where the scatter image is formed outside an outline of the image formed by the light emitted from the light emitter.

Abstract: A nitride semiconductor template includes a substrate, an AlN layer that is formed on the substrate and that includes Cl, and a nitride semiconductor layer formed on the AlN layer. In the AlN layer, a concentration of the Cl in a region on a side of the substrate is higher than that in a region on a side of the nitride semiconductor layer. Also, a light-emitting element includes the nitride semiconductor template, and a light-emitting layer formed on the nitride semiconductor template.

Abstract: There is provided a semiconductor manufacturing device, including: a processing vessel; a partition wall that divides at least a part of a space in the processing vessel into a growth section and a cleaning section; a substrate holding member disposed in the growth section; a source gas supply system that supplies a source gas into the growth section; a cleaning gas supply system that supplies a cleaning gas into the cleaning section; and a heater that heats the growth section and the cleaning section.

Abstract: A nitride semiconductor crystal producing method, includes growing a nitride semiconductor crystal over a seed crystal substrate, while applying an etching action to an outer end of the seed crystal substrate during the growing of the nitride semiconductor crystal.

Abstract: There is provided a method for manufacturing a nitride semiconductor template, including the steps of: growing and forming a buffer layer to be thicker than a peak width of a projection and in a thickness of not less than 11 nm and not more than 400 nm on a sapphire substrate formed by arranging conical or pyramidal projections on its surface in a lattice pattern; and growing and forming a nitride semiconductor layer on the buffer layer.

Abstract: There is provided a method for manufacturing a nitride semiconductor template constituted by forming a nitride semiconductor layer on a substrate, comprising: (a) preparing a pattern-substrate as the substrate, with a concavo-convex pattern formed on a front surface of the pattern-substrate, (b) forming a first layer by epitaxially growing a nitride semiconductor containing aluminum on the concavo-convex pattern of the pattern-substrate, in a thickness of not flattening a front surface; (c) applying annealing to the first layer; and (d) forming a second layer by epitaxially growing a nitride semiconductor containing aluminum so as to overlap on the first layer after performing (c), and in a thickness of flattening a front surface, and constituting the nitride semiconductor layer by the first layer and the second layer.