Patents by Inventor Hajime Sakamoto
Hajime Sakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10927226Abstract: The invention provides a prepreg comprising: a primary prepreg composed of reinforcing fibers and a resin composition (I) impregnating the interior of a reinforcing fiber layer formed from these fibers; and a surface layer composed of a resin composition (II) formed on one or both sides of the primary prepreg; wherein the resin composition (I) is an epoxy resin composition [B] containing at least an epoxy resin and a thermoplastic resin, and the resin composition (II) is an epoxy resin composition [A] containing at least an epoxy resin and conductive particles.Type: GrantFiled: September 25, 2013Date of Patent: February 23, 2021Assignee: TOHO TENAX CO., LTD.Inventors: Takaya Suzuki, Hajime Sakamoto, Toyoaki Ishiwata, Yoshitaka Umemoto
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Patent number: 10804191Abstract: A printed wiring board includes a first build-up layer having first insulating layer, conductor layer and via conductor, a second build-up layer formed on the first build-up layer and having second insulating layer, conductor layer and via conductor, a third build-up layer formed on the second build-up layer and having third insulating layer, conductor layer and via conductor, and a fourth build-up layer formed on the third build-up layer and having fourth insulating layer, conductor layer and via conductor. The first insulating layer has a thickness that is larger than a thickness of the second insulating layer, the thickness of the second insulating layer is larger than a thickness of the third insulating layer, the thickness of the second insulating layer is larger than a thickness of the fourth insulating layer, and the thickness of the fourth insulating layer is larger than the thickness of the third insulating layer.Type: GrantFiled: October 11, 2018Date of Patent: October 13, 2020Assignee: IBIDEN CO., LTD.Inventors: Hajime Sakamoto, Yoji Sawada
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Publication number: 20190109085Abstract: A printed wiring board includes a first build-up layer having first insulating layer, conductor layer and via conductor, a second build-up layer formed on the first build-up layer and having second insulating layer, conductor layer and via conductor, a third build-up layer formed on the second build-up layer and having third insulating layer, conductor layer and via conductor, and a fourth build-up layer formed on the third build-up layer and having fourth insulating layer, conductor layer and via conductor. The first insulating layer has a thickness that is larger than a thickness of the second insulating layer, the thickness of the second insulating layer is larger than a thickness of the third insulating layer, the thickness of the second insulating layer is larger than a thickness of the fourth insulating layer, and the thickness of the fourth insulating layer is larger than the thickness of the third insulating layer.Type: ApplicationFiled: October 11, 2018Publication date: April 11, 2019Applicant: IBIDEN CO., LTD.Inventors: Hajime SAKAMOTO, Yoji Sawada
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Publication number: 20190098752Abstract: A printed wiring board includes a first build-up layer including first insulating layer, conductor layer and via conductor, a second build-up layer formed on the first build-up layer and including second insulating layer, conductor layer and via conductor, and a third build-up layer formed on the second build-up layer and including third insulating layer, conductor layer and via conductor. The first via conductor has first via conductor diameter at interface between the first conductor layer and first via conductor, the second via conductor has second via conductor diameter at interface between the second conductor layer and second via conductor, and the third via conductor has third via conductor diameter at interface between the third conductor layer and third via conductor such that the first via conductor diameter is larger than the second via conductor diameter and that the second via conductor diameter is larger than the third via conductor diameter.Type: ApplicationFiled: September 27, 2018Publication date: March 28, 2019Applicant: IBIDEN CO., LTD.Inventors: Hajime Sakamoto, Yoji Sawada
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Patent number: 10186486Abstract: A wiring board includes conductor layers, core layers including a first core layer and a second core layer formed such that each of the first and second core layers includes a core material, an intermediate insulating layer formed between the first core layer and second core layer such that the intermediate insulating layer does not contain a core material, and an electronic component positioned between the first core layer and second core layer such that the electronic component is embedded in the intermediate insulating layer. At least one of the first and second core layers has a multilayer structure including a resin layer and an adhesive layer laminated on the resin layer such that the resin layer includes the core material and that the adhesive layer does not contain a core material, and the conductor layers include a conductor layer laminated on the adhesive layer of the multilayer structure.Type: GrantFiled: July 27, 2017Date of Patent: January 22, 2019Assignee: IBIDEN CO., LTD.Inventors: Hajime Sakamoto, Keisuke Shimizu
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Patent number: 10090238Abstract: A wiring substrate includes insulating layers including a first insulating layer and an outermost insulating layer such that the first insulating layer is positioned at one end of the insulating layers in a lamination direction and that the outermost insulating layer is positioned at the opposite end of the insulating layers in the lamination direction and includes a reinforcing material; conductive layers laminated on the insulating layers such that the conductive layers include an outermost conductive layer formed on the outermost insulating layer and including pads, and a semiconductor element accommodated in an accommodating portion of the first insulating layer. The insulating layers are formed such that the insulating layers do not contain a reinforcing material other than the outermost insulating layer.Type: GrantFiled: March 7, 2017Date of Patent: October 2, 2018Assignee: IBIDEN CO., LTD.Inventors: Hajime Sakamoto, Keisuke Shimizu
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Patent number: 9893016Abstract: A multilayer wiring board includes a main wiring board including insulation layers, first via conductors formed in the insulation layers, and a first conductive layer including first mounting pads such that the first mounting pads are positioned to mount a first electronic component and a second electronic component adjacent to each other on the main wiring board, and a wiring structure body mounted on the main wiring board such that the wiring structure body is positioned in an outermost insulation layer of the insulation layers, the wiring structure body including a second conductive layer which includes second mounting pads such that the second mounting pads are positioned to connect to the first electronic component and the second electronic component mounted on the main wiring board. The first via conductors are formed such that the first via conductors have diameters which increase in a same direction.Type: GrantFiled: October 12, 2015Date of Patent: February 13, 2018Assignee: IBIDEN CO., LTD.Inventors: Hajime Sakamoto, Yoshinori Shizuno, Shigeru Yamada, Takashi Kariya
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Publication number: 20180033732Abstract: A wiring board includes conductor layers, core layers including a first core layer and a second core layer formed such that each of the first and second core layers includes a core material, an intermediate insulating layer formed between the first core layer and second core layer such that the intermediate insulating layer does not contain a core material, and an electronic component positioned between the first core layer and second core layer such that the electronic component is embedded in the intermediate insulating layer. At least one of the first and second core layers has a multilayer structure including a resin layer and an adhesive layer laminated on the resin layer such that the resin layer includes the core material and that the adhesive layer does not contain a core material, and the conductor layers include a conductor layer laminated on the adhesive layer of the multilayer structure.Type: ApplicationFiled: July 27, 2017Publication date: February 1, 2018Applicant: IBIDEN CO., LTD.Inventors: HAJIME SAKAMOTO, KEISUKE SHIMIZU
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Patent number: 9837342Abstract: A multilayer wiring board includes a main wiring board which mounts a semiconductor component on a surface of the main wiring board, and a wiring structure body which is mounted to the main wiring board and is formed to be electrically connected to the semiconductor component. The wiring structure body includes conductive pads formed on a first side of the wiring structure body, a heat radiation component formed on a second side of the wiring structure body on the opposite side with respect to the first side, an insulation layer positioned between the conductive pads and the heat radiation component, and via conductors formed in the insulation layer such that each of the via conductors has a diameter which increases from the first side toward the second side of the wiring structure body.Type: GrantFiled: July 27, 2015Date of Patent: December 5, 2017Assignee: IBIDEN CO., LTD.Inventor: Hajime Sakamoto
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Publication number: 20170256470Abstract: A wiring substrate includes insulating layers including a first insulating layer such that the first insulating layer is positioned at one end of the insulating layers in lamination direction and has an accommodating portion through the first insulating layer, conductive layers laminated on the insulating layers and including a first conductive layer formed on one end side of the first insulating layer in the lamination direction and a second conductive layer formed on the opposite side, and a semiconductor element accommodated in the accommodating portion of the first insulating layer. The insulating layers include the first insulating layer including reinforcing material and a second insulating layer laminated on the first insulating layer such that the second insulating layer is covering the second conductive layer and the semiconductor element and filling gap formed between the first insulating layer and semiconductor element in the accommodating portion and does not contain reinforcing material.Type: ApplicationFiled: March 7, 2017Publication date: September 7, 2017Applicant: IBIDEN CO., LTD.Inventors: Hajime SAKAMOTO, Keisuke SHIMIZU
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Publication number: 20170256478Abstract: A wiring substrate includes insulating layers including a first insulating layer and an outermost insulating layer such that the first insulating layer is positioned at one end of the insulating layers in a lamination direction and that the outermost insulating layer is positioned at the opposite end of the insulating layers in the lamination direction and includes a reinforcing material; conductive layers laminated on the insulating layers such that the conductive layers include an outermost conductive layer formed on the outermost insulating layer and including pads, and a semiconductor element accommodated in an accommodating portion of the first insulating layer. The insulating layers are formed such that the insulating layers do not contain a reinforcing material other than the outermost insulating layer.Type: ApplicationFiled: March 7, 2017Publication date: September 7, 2017Applicant: IBIDEN CO., LTD.Inventors: Hajime Sakamoto, Keisuke Shimizu
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Patent number: 9711439Abstract: A printed wiring board includes an insulating layer including insulating material, and a conductor layer formed on a surface of the insulating layer and including conductor pads and conductor patterns such that the conductor pads are positioned to connect one or more electronic components and that the conductor patterns are formed between the conductor pads. The conductor patterns are formed such that each conductor pattern has a pattern width of 3 ?m or less and that the conductor patterns have a pattern interval of 3 ?m or less between adjacent conductor patterns, and the insulating layer has recess portions formed on the surface between the conductor patterns at least along the conductor patterns such that the recess portions have a depth in a range of 0.1 ?m to 2.0 ?m relative to a contact interface at which the conductor patterns and the insulating layer are in contact with each other.Type: GrantFiled: September 1, 2015Date of Patent: July 18, 2017Assignee: IBIDEN CO., LTD.Inventors: Hajime Sakamoto, Nobuya Takahashi
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Patent number: 9706663Abstract: A printed wiring board includes a first resin insulating layer, a first conductor pattern including first mounting pads formed on the first resin insulating layer, and a wiring structure positioned on the first resin insulating layer and including a second resin insulating layer and a second conductor pattern such that the second resin insulating layer and second conductor pattern are positioned adjacent to the first conductor pattern and that the second conductor pattern includes second mounting pads. The second mounting pads are embedded in the second resin insulating layer such that the second mounting pads have mounting surfaces exposed on an exposed surface of the second resin insulating layer, and the first mounting pads have mounting surfaces such that the mounting surfaces of the first and second mounting pads are formed on a same plane.Type: GrantFiled: August 31, 2015Date of Patent: July 11, 2017Assignee: IBIDEN CO., LTD.Inventors: Hajime Sakamoto, Masatoshi Kunieda, Makoto Terui, Takashi Kariya
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Patent number: 9420697Abstract: A method for manufacturing a printed wiring board includes forming an interlayer insulation layer on a conductive circuit, applying laser to a portion of the interlayer insulation layer such that an opening reaching to the conductive circuit is formed for a via conductor, subjecting the opening to a plasma treatment using a processing gas which includes a reactive gas including a fluorovinyl ether gas having a double bond of two carbon atoms and a fluoroalkyl ether group, forming an upper conductive circuit on the interlayer insulation layer, and forming a via conductor in the opening such that the via conductor connects the conductive circuit and the upper conductive circuit.Type: GrantFiled: June 28, 2012Date of Patent: August 16, 2016Assignees: IBIDEN Co., Ltd., National University Corporation Nagoya UniversityInventors: Yoshiyuki Iwata, Masaru Hori, Hajime Sakamoto
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Publication number: 20160105960Abstract: A multilayer wiring board includes a main wiring board including insulation layers, first via conductors formed in the insulation layers, and a first conductive layer including first mounting pads such that the first mounting pads are positioned to mount a first electronic component and a second electronic component adjacent to each other on the main wiring board, and a wiring structure body mounted on the main wiring board such that the wiring structure body is positioned in an outermost insulation layer of the insulation layers, the wiring structure body including a second conductive layer which includes second mounting pads such that the second mounting pads are positioned to connect to the first electronic component and the second electronic component mounted on the main wiring board. The first via conductors are formed such that the first via conductors have diameters which increase in a same direction.Type: ApplicationFiled: October 12, 2015Publication date: April 14, 2016Applicant: IBIDEN CO., LTD.Inventors: Hajime SAKAMOTO, Yoshinori SHIZUNO, Shigeru YAMADA, Takashi KARIYA
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Publication number: 20160095219Abstract: A printed wiring board includes a main wiring board having a main wiring pattern, and a sub wiring board mounted to the main board and having a sub wiring pattern such that the sub pattern electrically connects first and second electronic components, first conductor pads positioned to connect the first component to the main board and the sub board and having surfaces such that the first component is mounted onto the surfaces of the first pads via solder bumps, and second conductor pads positioned to connect the second component to the main board and the sub board and having surfaces such that the second component is mounted onto the surfaces of the second pads via solder bumps. The first and second pads are formed such that the surfaces of the first and second pads are formed on the same plane and have the same shape and the same size.Type: ApplicationFiled: September 25, 2015Publication date: March 31, 2016Applicant: IBIDEN CO., LTD.Inventors: Hajime SAKAMOTO, Ryojiro TOMINAGA
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Publication number: 20160066422Abstract: A printed wiring board includes a first resin insulating layer, a first conductor pattern including first mounting pads formed on the first resin insulating layer, and a wiring structure positioned on the first resin insulating layer and including a second resin insulating layer and a second conductor pattern such that the second resin insulating layer and second conductor pattern are positioned adjacent to the first conductor pattern and that the second conductor pattern includes second mounting pads. The second mounting pads are embedded in the second resin insulating layer such that the second mounting pads have mounting surfaces exposed on an exposed surface of the second resin insulating layer, and the first mounting pads have mounting surfaces such that the mounting surfaces of the first and second mounting pads are formed on a same plane.Type: ApplicationFiled: August 31, 2015Publication date: March 3, 2016Applicant: IBIDEN CO., LTD.Inventors: Hajime Sakamoto, Masatoshi Kunieda, Makoto Terui, Takashi Kariya
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Publication number: 20160066423Abstract: A printed wiring board includes an insulating layer including insulating material, and a conductor layer formed on a surface of the insulating layer and including conductor pads and conductor patterns such that the conductor pads are positioned to connect one or more electronic components and that the conductor patterns are formed between the conductor pads. The conductor patterns are formed such that each conductor pattern has a pattern width of 3 ?m or less and that the conductor patterns have a pattern interval of 3 ?m or less between adjacent conductor patterns, and the insulating layer has recess portions formed on the surface between the conductor patterns at least along the conductor patterns such that the recess portions have a depth in a range of 0.1 ?m to 2.0 ?m relative to a contact interface at which the conductor patterns and the insulating layer are in contact with each other.Type: ApplicationFiled: September 1, 2015Publication date: March 3, 2016Applicant: IBIDEN CO., LTD.Inventors: Hajime SAKAMOTO, Nobuya TAKAHASHI
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Publication number: 20160027725Abstract: A multilayer wiring board includes a main wiring board which mounts a semiconductor component on a surface of the main wiring board, and a wiring structure body which is mounted to the main wiring board and is formed to be electrically connected to the semiconductor component. The wiring structure body includes conductive pads formed on a first side of the wiring structure body, a heat radiation component formed on a second side of the wiring structure body on the opposite side with respect to the first side, an insulation layer positioned between the conductive pads and the heat radiation component, and via conductors formed in the insulation layer such that each of the via conductors has a diameter which increases from the first side toward the second side of the wiring structure body.Type: ApplicationFiled: July 27, 2015Publication date: January 28, 2016Applicant: IBIDEN CO., LTD.Inventor: Hajime SAKAMOTO
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Patent number: 9245838Abstract: A multilayer device has a resin layer, a semiconductor device positioned in the resin layer and including an electronic component and a passivation layer having an opening exposing an electrode of the electronic component, an intermediate layer including metal layers and formed in the opening of the passivation layer such that the intermediate layer is connected to the electrode of the electronic component, and a buildup layer formed on the resin layer and including an insulating layer and a via conductor formed in the insulating layer such that the via conductor is connected to the intermediate layer. The resin layer includes one or more resin material selected from the group consisting of a thermosetting resin material and a thermoplastic resin material.Type: GrantFiled: January 21, 2015Date of Patent: January 26, 2016Assignee: IBIDEN CO., LTD.Inventors: Hajime Sakamoto, Dongdong Wang