Patents by Inventor Hajime Sakamoto

Hajime Sakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050078919
    Abstract: A waveguide type optical module is provided which includes a temperature control element supported on pedestals inside a casing, and an optical waveguide provided on the temperature control element. The heating control element includes a plate having a heater or heat absorber provided on a non-heating side thereof or buried therein. The plate is supported on the pedestals with less than 30% of the area thereof being in contact with the plate. Because of such a structure, the waveguide type optical module has a good wavelength demultiplexing characteristic, and the temperature controller and control element for use in the optical module incur less occurrence of particle separation and shows a high homogeneity of plate-surface temperature distribution.
    Type: Application
    Filed: January 16, 2003
    Publication date: April 14, 2005
    Applicant: IBIDEN CO., LTD
    Inventors: Mikio Mori, Hajime Sakamoto, Yasutaka Ito
  • Publication number: 20040168825
    Abstract: A multilayer printed circuit board has an IC chip 20 included in a core substrate 30 in advance and a transition layer 38 provided on a pad 24 of the IC chip 20. Due to this, it is possible to electrically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on the die pad 24, it is possible to prevent resin residues on the pad 24 and to improve connection characteristics between the pad 24 and a via hole 60 and reliability.
    Type: Application
    Filed: March 4, 2004
    Publication date: September 2, 2004
    Inventors: Hajime Sakamoto, Tadashi Sugiyama, Dongdong Wang, Takashi Kariya
  • Publication number: 20040014317
    Abstract: A transition layer 38 is provided on a die pad 22 of an IC chip 20 and integrated into a multilayer printed circuit board 10. Due to this, it is possible to electrically connect the IC chip 20 to the multilayer printed circuit board 10 without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on an aluminum pad 24, it is possible to prevent a resin residue on the pad 24 and to improve connection characteristics between the die pad 24 and a via hole 60 and reliability.
    Type: Application
    Filed: March 21, 2003
    Publication date: January 22, 2004
    Inventors: Hajime Sakamoto, Dongdong Wang
  • Patent number: 6586276
    Abstract: A passivation layer is formed over a semiconductor wafer carrying a plurality of independent circuits. The passivation layer includes openings to expose bond pads on the wafer. A conductive adhesion material is then deposited over the wafer and an optional protection layer is deposited over the conductive adhesion material. The wafer is then cut up into individual microelectronic dice. During a subsequent packaging process, one or more microelectronic dice are fixed within a package core to form a die/core assembly. Expanded bond pads are then formed over the die/core assembly. The adhesion material on each die enhances the adhesion between the expanded bond pads and the passivation material on the die. One or more metal layers are then built up over the die/core assembly to provide, for example, conductive communication between the terminals of the die and the external contacts/leads of the package.
    Type: Grant
    Filed: July 11, 2001
    Date of Patent: July 1, 2003
    Assignee: Intel Corporation
    Inventors: Steven Towle, Hajime Sakamoto, Dongdong Wang
  • Publication number: 20030015342
    Abstract: A multilayer printed circuit board has an IC chip 20 included in a core substrate 30 in advance and a transition layer 38 provided on a pad 24 of the IC chip 20. Due to this, it is possible to electrically connect the IC chip to the multilayer printed circuit board without using lead members and a sealing resin. Also, by providing the transition layer 38 made of copper on the die pad 24, it is possible to prevent resin residues on the pad 24 and to improve connection characteristics between the pad 24 and a via hole 60 and reliability.
    Type: Application
    Filed: July 17, 2002
    Publication date: January 23, 2003
    Inventors: Hajime Sakamoto, Tadashi Sugiyama, Dongdong Wang, Takashi Kariya
  • Publication number: 20030013232
    Abstract: A passivation layer is formed over a semiconductor wafer carrying a plurality of independent circuits. The passivation layer includes openings to expose bond pads on the wafer. A conductive adhesion material is then deposited over the wafer and an optional protection layer is deposited over the conductive adhesion material. The wafer is then cut up into individual microelectronic dice. During a subsequent packaging process, one or more microelectronic dice are fixed within a package core to form a die/core assembly. Expanded bond pads are then formed over the die/core assembly. The adhesion material on each die enhances the adhesion between the expanded bond pads and the passivation material on the die. One or more metal layers are then built up over the die/core assembly to provide, for example, conductive communication between the terminals of the die and the external contacts/leads of the package.
    Type: Application
    Filed: July 11, 2001
    Publication date: January 16, 2003
    Applicant: Intel Corporation
    Inventors: Steven Towle, Hajime Sakamoto, Dongdong Wang