Abstract: A phase-change material (PCM) switching device includes: a base dielectric layer over a semiconductor substrate; a first heater element disposed on the base dielectric layer, the first heater element comprising a first metal element characterized by a first coefficient of thermal expansion (CTE); a second heater element disposed on the first heater element, the second heater element comprising a second metal element characterized by a second CTE larger than the first CTE; a first metal pad and a second metal pad; and a PCM region comprising a PCM operable to switch between an amorphous state and a crystalline state in response to heat generated by the first heater element and the second heater element, wherein the PCM region is disposed above a top surface of the second heater element, and an air gap surrounds the first heater element and the second heater element from three sides.

Abstract: A semiconductor device includes a substrate, a first well, a second well, a metal gate, a poly gate, a source region, and a drain region. The first well and the second well are within the substrate. The metal gate is partially over the first well. The poly gate is over the second well. The poly gate is separated from the metal gate, and a width ratio of the poly gate to the metal gate is in a range from about 0.1 to about 0.2. The source region and the drain region are respectively within the first well and the second well.

Abstract: A pyroelectric generator may be included in the same semiconductor device as a radio frequency (RF) switch (e.g., a phase-change material (PCM) RF switch and/or other types of RF switch). The pyroelectric generator includes a pyroelectric material layer between two electrodes. The pyroelectric generator is configured to scavenge thermal energy that is generated during the operation of the RF switch, and to convert the thermal energy into electrical energy that may be stored and reused.

Abstract: A dielectric isolation layer having a top surface may be formed over a substrate. A heater line, a phase change material (PCM) line, and an in-process conductive barrier plate may be formed over the dielectric isolation layer. An electrode material layer may be formed over the in-process conductive barrier plate. The electrode material layer and the in-process conductive barrier plate may be patterned such that patterned portions of the in-process conductive barrier plate include a first conductive barrier plate contacting a first area of a top surface of the PCM line, and a second conductive barrier plate contacting a second area of the top surface of the PCM line, and patterned portions of the electrode material layer include a first electrode contacting the first conductive barrier plate and a second electrode contacting the second conductive barrier plate.

Abstract: The present disclosure relates to an integrated chip including a first dielectric layer overlying a substrate and a first conductive interconnect within the first dielectric layer. A bonding layer is over the first dielectric layer. The bonding layer includes a bonding dielectric layer and a bonding interconnect in the bonding dielectric layer. A first charged dielectric layer is along a bottom of the first dielectric layer. A second charged dielectric layer is along a top of the first dielectric layer. The first charged dielectric layer and the second charged dielectric layer have a same polarity.

Abstract: A method of forming a memory device according to the present disclosure includes forming a trench in a first substrate of a first wafer, depositing a data-storage element in the trench, performing a thermal treatment to the first wafer to improve a crystallization in the data-storage element, forming a first redistribution layer over the first substrate, forming a transistor in a second substrate of a second wafer, forming a second redistribution layer over the second substrate, and bonding the first wafer with the second wafer after the performing of the thermal treatment. The data-storage element is electrically coupled to the transistor through the first and second redistribution layers.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a substrate. The substrate includes a metal layer, a device layer disposed over the metal layer, and an insulating layer disposed vertically between the metal layer and the device layer. A semiconductor device is disposed on the device layer. An interlayer dielectric (ILD) layer is disposed over the semiconductor device and the substrate.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a memory cell stack over a substrate. The memory cell stack includes a top electrode. A sidewall spacer structure is formed around the memory cell stack. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. A dielectric structure is formed over the sidewall spacer structure. A first etch process is performed on the dielectric structure and the second sidewall spacer layer to define an opening above the top electrode. The second sidewall spacer layer and the dielectric structure are etched at a higher rate than the protective sidewall spacer layer during the first etch process. A top electrode via is formed within the opening.

Abstract: A memory device includes a bottom electrode, a magnetic tunnel junction (MTJ) stack, a top electrode, and a sidewall spacer. The MTJ stack is over the bottom electrode. The top electrode is over the MTJ stack. The sidewall spacer laterally surrounds the MTJ stack and the top electrode. The sidewall spacer has an outermost sidewall laterally set back from an outermost sidewall of the bottom electrode.

Abstract: The present disclosure relates to a magneto-resistive random access memory (MRAM) cell having an extended upper electrode, and a method of formation the same. In some embodiments, the MRAM cell has a magnetic tunnel junction (MTJ) arranged over a conductive lower electrode. Two protection layers sequentially surround a sidewall of the MTJ. The two protection layers have etch selectivity over one another.

Abstract: A semiconductor device includes a first dielectric layer, a second dielectric layer and a memory device. The second dielectric layer includes a first layer and a second layer. The memory device includes a first conductive structure under the first dielectric layer, a second conductive structure over the second dielectric layer, and a memory cell between the first and the second dielectric layers. The memory cell includes a bottom electrode via, a bottom electrode over the bottom electrode via, a top electrode over the bottom electrode, a top electrode via over the top electrode, and a MTJ between the top electrode and the bottom electrode. The second layer of the second dielectric layer surrounds sidewalls of the top electrode via entirely. The first layer of the second dielectric layer surrounds sidewalls of the bottom electrode entirely, sidewalls of the MTJ entirely, and sidewalls of the top electrode entirely.

Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.

Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a an inter-layer dielectric (ILD) structure laterally surrounding a conductive interconnect. A dielectric protection layer is disposed over the ILD structure and a passivation layer is disposed over the dielectric protection layer. The passivation layer includes a protrusion extending outward from an upper surface of the passivation layer. A bottom electrode continuously extends from over the passivation layer to between sidewalls of the passivation layer. A data storage element is over the bottom electrode and a top electrode is over the data storage element.

Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.

Abstract: A semiconductor feature includes: a semiconductor substrate; a dielectric structure and a semiconductor device disposed on the semiconductor substrate; an interconnecting structure disposed in the dielectric structure and connected to the semiconductor device; an STI structure disposed in the semiconductor substrate and surrounding the semiconductor device; two DTI structures penetrating the semiconductor substrate and the STI structure and surrounding the semiconductor device; a passivation structure connected to the semiconductor substrate and the DTI structures and located opposite to the interconnecting structure; and a conductive structure surrounded by the passivation structure, penetrating the semiconductor substrate and the STI structure into the dielectric structure, located between the DTI structures and electrically connected to the semiconductor device via the interconnecting structure.

Abstract: A first die includes a first substrate and a first interconnect structure. A second die is bonded to the first die and includes a second substrate and a second interconnect structure, such that the first and second interconnect structures are arranged between the first and second substrates. A redistribution layer (RDL) stack is arranged on an outer side of the first die opposite the first interconnect structure. A heat path includes a through substrate via (TSV) extending from a conductive layer in the first interconnect structure, through the first substrate, and into the RDL stack. An RDL dielectric material is included in the RDL stack and separates the heat path from an ambient environment. A thermal conductivity of the RDL dielectric is over twenty times a thermal conductivity of an interconnect dielectric material of the first interconnect structure or of the second interconnect structure.

Abstract: An MRAM memory cell includes a substrate and a transistor. The transistor includes: first and second source regions; a drain region between the first and second source regions; a first channel region between the drain region and the first source region; a second channel region between the drain region and the second source region; a first gate structure over the first channel region; and a second gate structure over the second channel region. A magnetic tunnel junction is overlying the transistor. The drain region is coupled to the magnetic tunnel junction. A first metal layer is overlying the transistor, and a second metal layer is overlying the first metal layer. The second and first metal layers couple a common source line signal to the first and second source regions of the MRAM memory cell and to those of a neighboring MRAM memory cell.

Abstract: A semiconductor device according to the present disclosure includes a first conductive feature and a second conductive feature in a first dielectric layer, a buffer layer over the first dielectric layer, a second dielectric layer over the buffer layer, a first bottom via extending through the buffer layer and the second dielectric layer, a second bottom via extending through the buffer layer and the second dielectric layer, a first bottom electrode disposed on the first bottom via, a second bottom electrode disposed on the second bottom via, a first magnetic tunnel junction (MTJ) stack over the first bottom electrode, and a second MTJ stack over the second bottom electrode. The first MTJ stack and the second MTJ stack have a same thickness. The first MTJ stack has a first width and the second MTJ stack has a second width greater than the first width.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate. The bottom electrode has a first thickness along an outermost edge and a second thickness between the outermost edge and a lateral center of the bottom electrode. The first thickness is larger than the second thickness. A data storage structure is over the bottom electrode and a top electrode is over the data storage structure.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a plurality of doped regions located in a substrate; a first dielectric layer located on the substrate; a plurality of first contacts and second contacts located in the first dielectric layer and connected to the plurality of doped regions; a second dielectric layer located on the first dielectric layer; a memory element located in the second dielectric layer, the memory element being electrically connected to the second contact; and a plurality of conductive interconnects located in the second dielectric layer. The conductive interconnects being electrically connected to the plurality of first contacts, and a top surface of the conductive interconnects being at a same level as a top surface of the memory element. A method of fabricating a semiconductor device, and a semiconductor structure having a semiconductor device are also provided.