Patents by Inventor Hak-Lay Chuang

Hak-Lay Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240381666
    Abstract: A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line; and forming a second metal line in the first trench to contact the first metal line.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Harry-Hak-Lay Chuang, Sheng-Huang Huang, Shih-Chang Liu, Chern-Yow Hsu
  • Publication number: 20240379656
    Abstract: The present disclosure relates to an integrated chip including a first metal layer over a substrate. A second metal layer is over the first metal layer. An ionic crystal layer is between the first metal layer and the second metal layer. A metal oxide layer is between the first metal layer and the second metal layer. The first metal layer, the second metal layer, the ionic crystal layer, and the metal oxide layer are over a transistor device that is arranged along the substrate.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Yi Ching Ong, Kuen-Yi Chen, Yi-Hsuan Chen, Kuo-Ching Huang, Harry-Hak-Lay Chuang
  • Publication number: 20240379486
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a substrate. A semiconductor device is disposed on the substrate. An interlayer dielectric (ILD) structure is disposed over the substrate and the semiconductor device. A first intermetal dielectric (IMD) structure is disposed over the substrate and the ILD structure. An opening is disposed in the first IMD structure. The opening overlies at least a portion of the semiconductor device.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 14, 2024
    Inventors: Harry-Hak-Lay Chuang, Hsin Fu Lin, Shiang-Hung Huang, Tsung-Hao Yeh
  • Publication number: 20240371798
    Abstract: A semiconductor structure may be located over a substrate, and may include a parallel connection of a first component and a second component. The first component includes a series connection of a diode and a capacitor that is selected from a metal-ferroelectric-metal capacitor and a metal-antiferroelectric-metal capacitor. The second component includes a battery structure. The semiconductor structure may be used as a combination of an energy harvesting device and an energy storage structure that utilizes heat from adjacent semiconductor devices or from other heat sources.
    Type: Application
    Filed: July 21, 2024
    Publication date: November 7, 2024
    Inventors: Kuen-Yi Chen, Yi Ching Ong, Kuo-Ching Huang, Harry-Hak-Lay Chuang
  • Publication number: 20240371884
    Abstract: In some embodiments, the present disclosure relates to a device that includes a silicon-on-insulator (SOI) substrate. A first semiconductor device is disposed on a frontside of the SOI substrate. An interconnect structure is arranged over the frontside of the SOI substrate and coupled to the first semiconductor device. A shallow trench isolation (STI) structure is arranged within the frontside of the SOI substrate and surrounds the first semiconductor device. First and second deep trench isolation (DTI) structures extend from the STI structure to an insulator layer of the SOI substrate. Portions of the first and second DTI structures are spaced apart from one another by an active layer of the SOI substrate. A backside through substrate via (BTSV) extends completely through the SOI substrate from a backside to the frontside of the SOI substrate. The BTSV is arranged directly between the first and second DTI structures.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: Harry-Hak-Lay Chuang, Wen-Tuo Huang, Hsin Fu Lin, Wei Cheng Wu
  • Publication number: 20240371459
    Abstract: A magnetoresistive random access memory (MRAM) device is provided. The MRAM device includes a main magnetic tunnel junction (MTJ) array comprising a plurality of memory cells configured to store memory data and a reference MTJ array comprising a plurality of reference cells having MTJ structures. The MRAM device further includes a controller operatively associated with the main MTJ array and the reference MTJ array. The controller is configured to receive a gross resistance of the reference MTJ array being related to a strength of an external magnetic field, determine whether the external magnetic field is fatal based on the received gross resistance of the reference MTJ array and a pre-determined threshold, and provide notification indicating that the memory data stored in the main MTJ array is untrustworthy if it is determined that the external magnetic field around the MRAM device is fatal.
    Type: Application
    Filed: July 21, 2024
    Publication date: November 7, 2024
    Inventors: Harry-Hak-Lay Chuang, Yuan-Jen Lee, Tien-Wei Chiang, Yi-Chun Shih
  • Publication number: 20240371681
    Abstract: A semiconductor feature includes: a semiconductor substrate; a dielectric structure and a semiconductor device disposed on the semiconductor substrate; an interconnecting structure disposed in the dielectric structure and connected to the semiconductor device; an STI structure disposed in the semiconductor substrate and surrounding the semiconductor device; two DTI structures penetrating the semiconductor substrate and the STI structure and surrounding the semiconductor device; a passivation structure connected to the semiconductor substrate and the DTI structures and located opposite to the interconnecting structure; and a conductive structure surrounded by the passivation structure, penetrating the semiconductor substrate and the STI structure into the dielectric structure, located between the DTI structures and electrically connected to the semiconductor device via the interconnecting structure.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay CHUANG, Chung-Jen HUANG, Wen-Tuo HUANG, Wei-Cheng WU
  • Patent number: 12136627
    Abstract: In some embodiments, the present disclosure relates to a device that includes a silicon-on-insulator (SOI) substrate. A first semiconductor device is disposed on a frontside of the SOI substrate. An interconnect structure is arranged over the frontside of the SOI substrate and coupled to the first semiconductor device. A shallow trench isolation (STI) structure is arranged within the frontside of the SOI substrate and surrounds the first semiconductor device. First and second deep trench isolation (DTI) structures extend from the STI structure to an insulator layer of the SOI substrate. Portions of the first and second DTI structures are spaced apart from one another by an active layer of the SOI substrate. A backside through substrate via (BTSV) extends completely through the SOI substrate from a backside to the frontside of the SOI substrate. The BTSV is arranged directly between the first and second DTI structures.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: November 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Wen-Tuo Huang, Hsin Fu Lin, Wei Cheng Wu
  • Publication number: 20240365682
    Abstract: A MRAM device includes a substrate, a first bottom electrode, a first MTJ stack, a first spacer, a topography-smoothing layer and a second ILD layer. The substrate includes a first ILD layer having a metal line. The first MTJ stack is over the first bottom electrode. The first spacer surrounds sidewalls of the first MTJ stack. The topography-smoothing layer extends over a top surface of the first ILD layer, along sidewalls of the first bottom electrode the first spacer. The topography-smoothing layer has a top portion over the first MTJ stack and a first side portion laterally surrounding the first spacer. The first side portion has a maximal lateral thickness greater than a maximal vertical thickness of the top portion. The second ILD layer is over the topography-smoothing layer and has a material different from a material of the topography-smoothing layer.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay CHUANG, Sheng-Chang CHEN, Hung Cho WANG, Sheng-Huang HUANG
  • Patent number: 12133470
    Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nth metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)th metal layer over the top electrode. The first width is greater than the third width.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CPMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Kuei-Hung Shen, Chern-Yow Hsu, Shih-Chang Liu
  • Publication number: 20240339144
    Abstract: An exemplary magnetoresistive random-access memory (MRAM) cell is configured to store more than one bit. The MRAM cell includes a first magnetic tunneling junction (MTJ) and a second MTJ connected in parallel. The first MTJ has a first diameter, the second MTJ has a second diameter, and the second diameter is less than the first diameter. The MRAM cell further includes a transistor connected to the first MTJ and the second MTJ, a bit line connected to the first MTJ and the second MTJ, a word line connected to the transistor, and a source line connected to the transistor. A method of writing to the MRAM cell can include supplying one or more write voltages to the MRAM cell (e.g., having different levels) depending on an initial memory state and a desired memory state of the MRAM cell.
    Type: Application
    Filed: August 3, 2023
    Publication date: October 10, 2024
    Inventors: Harry-Hak-Lay Chuang, Ching-Huang Wang, Hung Cho Wang, Tien-Wei Chiang, Wen-Chun You
  • Patent number: 12107001
    Abstract: A semiconductor feature includes: a semiconductor substrate; a dielectric structure and a semiconductor device disposed on the semiconductor substrate; an interconnecting structure disposed in the dielectric structure and connected to the semiconductor device; an STI structure disposed in the semiconductor substrate and surrounding the semiconductor device; two DTI structures penetrating the semiconductor substrate and the STI structure and surrounding the semiconductor device; a passivation structure connected to the semiconductor substrate and the DTI structures and located opposite to the interconnecting structure; and a conductive structure surrounded by the passivation structure, penetrating the semiconductor substrate and the STI structure into the dielectric structure, located between the DTI structures and electrically connected to the semiconductor device via the interconnecting structure.
    Type: Grant
    Filed: August 7, 2023
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Chung-Jen Huang, Wen-Tuo Huang, Wei-Cheng Wu
  • Publication number: 20240321635
    Abstract: The present disclosure relates to an integrated chip in some embodiments. The integrated chip includes an inter-level dielectric (ILD) laterally surrounding a memory device. One or more sidewall spacers are arranged along opposing sides of the memory device. The one or more sidewall spacers have a bottom surface over a bottom of the memory device. An etch stop layer is disposed on the one or more sidewall spacers and along the opposing sides of the memory device. An upper interconnect is arranged directly over the memory device, a top surface of the one or more sidewall spacers, and an upper surface of the etch stop layer.
    Type: Application
    Filed: May 20, 2024
    Publication date: September 26, 2024
    Inventors: Sheng-Huang Huang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen
  • Publication number: 20240290786
    Abstract: Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.
    Type: Application
    Filed: May 9, 2024
    Publication date: August 29, 2024
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Li-Feng Teng, Li-Jung Liu
  • Patent number: 12068313
    Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a first gate structure on a first side of an active area and a second gate structure on a second side of the active area, where the first gate structure and the second gate structure share the active area. A method of forming the semiconductor arrangement includes forming a deep implant of the active area before forming the first gate structure, and then forming a shallow implant of the active area. Forming the deep implant prior to forming the first gate structure alleviates the need for an etching process that degrades the first gate structure. The first gate structure thus has a desired configuration and is able to be formed closer to other gate structures to enhance device density.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Harry-Hak-Lay Chuang, Wei Cheng Wu, Shih-Chang Liu, Ming Chyi Liu
  • Patent number: 12069963
    Abstract: A MRAM device includes a substrate, a first bottom electrode, a first MTJ stack, a first spacer, a topography-smoothing layer and a second ILD layer. The substrate includes a first ILD layer having a metal line. The first MTJ stack is over the first bottom electrode. The first spacer surrounds sidewalls of the first MTJ stack. The topography-smoothing layer extends over a top surface of the first ILD layer, along sidewalls of the first bottom electrode the first spacer. The topography-smoothing layer has a top portion over the first MTJ stack and a first side portion laterally surrounding the first spacer. The first side portion has a maximal lateral thickness greater than a maximal vertical thickness of the top portion. The second ILD layer is over the topography-smoothing layer and has a material different from a material of the topography-smoothing layer.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Sheng-Chang Chen, Hung Cho Wang, Sheng-Huang Huang
  • Publication number: 20240250089
    Abstract: A layer stack including a first bonding dielectric material layer, a dielectric metal oxide layer, and a second bonding dielectric material layer is formed over a top surface of a substrate including a substrate semiconductor layer. A conductive material layer is formed by depositing a conductive material over the second bonding dielectric material layer. The substrate semiconductor layer is thinned by removing portions of the substrate semiconductor layer that are distal from the layer stack, whereby a remaining portion of the substrate semiconductor layer includes a top semiconductor layer. A semiconductor device may be formed on the top semiconductor layer.
    Type: Application
    Filed: April 5, 2024
    Publication date: July 25, 2024
    Inventors: Harry-Hak-Lay Chuang, Wei-Cheng Wu, Chien Hung Liu, Hsin Fu Lin, Hsien Jung Chen, Henry Wang, Tsung-Hao Yeh, Kuo-Ching Huang
  • Publication number: 20240250116
    Abstract: An integrated circuit (IC) device comprises a high voltage semiconductor device (HVSD) on a frontside of a semiconductor body and further comprises an electrode on a backside of the semiconductor body opposite the frontside. The HVSD may for example, be a transistor or some other suitable type of semiconductor device. The electrode has one or more gaps directly beneath the HVSD. The one or more gaps enhance the effectiveness of the electrode for improving the breakdown voltage of the HVSD.
    Type: Application
    Filed: February 15, 2024
    Publication date: July 25, 2024
    Inventors: Harry-Hak-Lay Chuang, Hsin Fu Lin, Tsung-Hao Yeh
  • Publication number: 20240222332
    Abstract: Bonded wafer device structures, such as a wafer-on-wafer (WoW) structures, and methods of fabricating bonded wafer device structures, including an array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure. The array of contact pads formed in an interconnect level of at least one wafer may have an array pattern that corresponds to an array pattern of contact pads that is subsequently formed over a surface of the bonded wafer structure. The array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure may enable improved testing of individual wafers, including circuit probe testing, prior to the wafer being stacked and bonded to one or more additional wafers to form a bonded wafer structure.
    Type: Application
    Filed: March 14, 2024
    Publication date: July 4, 2024
    Inventors: Harry-Hak-Lay Chuang, Wei-Cheng Wu, Wen-Tuo Huang
  • Patent number: 12027420
    Abstract: The present disclosure relates to an integrated chip in some embodiments. The integrated chip includes a memory device disposed over a lower interconnect within one or more lower inter-level dielectric (ILD) layers over a substrate. An upper ILD layer laterally surrounds the memory device. An etch stop layer is disposed along a sidewall of the memory device and over an upper surface of the one or more lower ILD layers. An upper interconnect is arranged along opposing sides of the memory device. The upper interconnect rests of an upper surface of the etch stop layer. The upper surface of the etch stop layer is vertically below a top of the memory device.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: July 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Huang Huang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Hung Cho Wang, Sheng-Chang Chen