Abstract: A vertical IGBT device is disclosed. The vertical IGBT structure includes an active MOSFET cell array formed in an active region at a front side of a semiconductor substrate of a first conductivity type. One or more column structures of a second conductivity type concentrically surround the active MOSFET cell array. Each column structure includes a column trench and a deep column region. The deep column region is formed by implanting implants of the second conductivity type into the semiconductor substrate through the floor of the column trench. Dielectric side wall spacers are formed on the trench side walls except a bottom wall of the trench and the column trench is filled with poly silicon of the second conductivity type. One or more column structures are substantially deeper than the active MOSFET cell array.

Abstract: Semiconductor devices and methods of fabrication are provided. The semiconductor device includes a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD) to control charge injection by lowering carrier storage. The device can have a first conductivity type semiconductor substrate, and a drift region that includes a doped buffer region, a doped middle region and a doped field stop region or carrier storage region. The device can also include a second conductivity type shield region including a deep junction encircling (or substantially laterally beneath) the buffer region and a second conductivity type shallow junction anode region in electrical contact with a second conductivity type anode electrode. The deep junction can have a range of doping concentrations surrounding the buffer regions to deplete buffer charge laterally as well as vertically to prevent premature device breakdown. The first conductivity type may be N type and the second conductivity type may be P type.

Abstract: The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom electrode of the semiconductor device. The super junction drift region includes a plurality of pillars having P type conductivity, formed in the super junction drift region, which are surrounded by an N type material of the super junction drift region.

Abstract: A field stop insulated gate bipolar transistor (IGBT) fabricated without back-side laser dopant activation or any process temperatures over 450° C. after fabrication of front-side IGBT structures provides activated injection regions with controlled dopant concentrations. Injection regions may be formed on or in a substrate by epitaxial growth or ion implants and diffusion before growth of N field stop and drift layers and front-side fabrication of IGBT active cells. Back-side material removal can expose the injection region(s) for electrical connection to back-side metal. Alternatively, after front-side fabrication of IGBT active cells, back-side material removal can expose the field stop layer (or injection regions) and sputtering using a silicon target with a well-controlled doping concentration can form hole or electron injection regions with well-controlled doping concentration.

Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

Abstract: A self-aligned p+ contact MOSFET device is provided. A process to manufacture the device includes forming oxide plugs on top of gate trenches, conducting uniform silicon mesa etch back, and forming oxide spacers to form contact trenches.

Abstract: Semiconductor devices and methods of fabrication are provided. The semiconductor device includes a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD) to control charge injection by lowering carrier storage. The device can have a first conductivity type semiconductor substrate, and a drift region that includes a doped buffer region, a doped middle region and a doped field stop region or carrier storage region. The device can also include a second conductivity type shield region including a deep junction encircling (or substantially laterally beneath) the buffer region and a second conductivity type shallow junction anode region in electrical contact with a second conductivity type anode electrode. The deep junction can have a range of doping concentrations surrounding the buffer regions to deplete buffer charge laterally as well as vertically to prevent premature device breakdown. The first conductivity type may be N type and the second conductivity type may be P type.

Abstract: The present invention provides semiconductor devices with super junction drift regions that are capable of blocking voltage. A super junction drift region is an epitaxial semiconductor layer located between a top electrode and a bottom electrode of the semiconductor device. The super junction drift region includes a plurality of pillars having P type conductivity, formed in the super junction drift region, which are surrounded by an N type material of the super junction drift region.

Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

Abstract: Building blocks for a smart device such as a thermostat include a user interface (UI) unit and a terminal (TML) unit. A UI unit may support one or more input data from a user and/or sensors and/or one or more control terminals. The UI unit may process each input datum or a combination of the input data, generate a control signal to one or more control terminals based on the processing, and send the control signal to one or more control terminals over a communication channel. A terminal unit, which may consist of one or more control terminals, transforms the received control signal into one or more controls to one or more associated environmental generators. One or more UI units may control one or more controlled apparatuses in conjunction with a mobile app to allow a unified user experience.

Abstract: A MOSFET device structure is formed on a semiconductor wafer. The structure includes an array of plurality of MOS gate trenches and self-aligned p+ contact trenches that are formed in a p body region. Trench depth of MOS gate trenches are deeper than the self-aligned p+ contact trenches. P doped shield regions are formed under each MOS gate trench.

Abstract: A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

Abstract: A smart electrical plug supports one or more electrical outlets and one or more universal serial bus (USB) outlets for charging electrical devices. Electrical power consumed through the one or more electrical outlets may be measured individually or in combination and reported via a wireless communication channel. The smart electrical plug may be implemented by a plurality of printed circuit board assemblies and distributed within a housing to reduce the effects of heat dissipation. The smart electrical plug may further reduce heat dissipation by utilizing one or more electrical circuit approaches.

Abstract: A vertical IGBT device is provided. The vertical IGBT device includes a substrate having a first conductivity type. A drift region of the first conductivity type formed on the top surface of the substrate. The bottom surface of the substrate is patterned to have an array of mesas and grooves. The mesas and the grooves are formed in an alternating fashion so that each mesa is separated from the other by a groove including a groove surface. In the groove surface, a top buffer region of the first conductivity type and a bottom buried region of a second conductivity type are formed extending laterally between the mesas adjacent each groove surface. Each mesa includes an upper region of the first conductivity and a lower region of the second conductivity.

Abstract: A vertical IGBT device is provided. The vertical IGBT device includes a substrate having a first conductivity type. A drift region of the first conductivity type formed on the top surface of the substrate. The bottom surface of the substrate is patterned to have an array of mesas and grooves. The mesas and the grooves are formed in an alternating fashion so that each mesa is separated from the other by a groove including a groove surface. In the groove surface, a top buffer region of the first conductivity type and a bottom buried region of a second conductivity type are formed extending laterally between the mesas adjacent each groove surface. Each mesa includes an upper region of the first conductivity and a lower region of the second conductivity.

Abstract: A thermostatic radiator valve (TRV) assembly or automatic temperature balanced actuator (ABA) assembly controls a manifold assembly through a push pin bearing mechanism. The push pin bearing mechanism comprises a push pin that moves in a linear direction responsive to rotational movement of a motor gear that is coupled through a helical gear. Rotational movement of the push pin is prevented by a ball bearing assembly. Movement of the push pin is transferred to a manifold pin, which in turn, controls the manifold assembly. Because the push pin moves in a linear rather than a rotational fashion, erosion of the mated manifold pin is substantially reduced with respect to transitional approaches.

Abstract: A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

Abstract: Building blocks for a smart device such as a thermostat include a user interface (UI) unit and a terminal (TML) unit. A UI unit may support one or more input data from a user and/or sensors and/or one or more control terminals. The UI unit may process each input datum or a combination of the input data, generate a control signal to one or more control terminals based on the processing, and send the control signal to one or more control terminals over a communication channel. A terminal unit, which may consist of one or more control terminals, transforms the received control signal into one or more controls to one or more associated environmental generators. One or more UI units may control one or more controlled apparatuses in conjunction with a mobile app to allow a unified user experience.

Abstract: A thermostatic radiator valve (TRV) assembly or automatic temperature balanced actuator (ABA) assembly controls a manifold assembly through a push pin bearing mechanism. The push pin bearing mechanism comprises a push pin that moves in a linear direction responsive to rotational movement of a motor gear that is coupled through a helical gear. Rotational movement of the push pin is prevented by a ball bearing assembly. Movement of the push pin is transferred to a manifold pin, which in turn, controls the manifold assembly. Because the push pin moves in a linear rather than a rotational fashion, erosion of the mated manifold pin is substantially reduced with respect to transitional approaches.

Abstract: A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.