Abstract: Circuits and methods for controlling data I/O operations in semiconductor memory devices to provide variable data I/O widths for read, write and active memory operations. Circuits and methods for selectively controlling a data width of a data I/O buffer “on the fly” to enable variable data I/O widths during memory access operations.

Abstract: A semiconductor memory device for use in a multiprocessor system includes at least two shared memory areas and a row decoder. The at least two shared memory areas are accessible in common by multiple processors of the multiprocessor system through different ports, and assigned based on predetermined memory capacity to a portion of a memory cell array. The row decoder is configured to form a continuous address map for remaining memory portions of the at least two shared memory areas to be dedicated to one port. Each remaining memory portion does not include a corresponding data transfer portion within each shared memory area.

Abstract: A semiconductor memory device for use in a multiprocessor system includes a shared memory area and a reset signal generator. The shared memory area is accessible by the processors of the multiprocessor system through different ports, and is assigned to a portion of a memory cell array. The reset signal generator is configured to provide a reset enable signal to a processor, predetermined as a slave processor among the multiple processors, for a predetermined time after an initial booting of the multiprocessor system. The reset signal generator also provides a reset disable signal to the slave processor after the predetermined time lapses.

Abstract: Example embodiments relate to a semiconductor memory system which may include a volatile memory and a non-volatile memory that share a common bus, and a method for controlling the operation of the non-volatile memory. The semiconductor memory system may include a non-volatile memory and a memory controller. The non-volatile memory may include a buffer memory that temporarily stores data to be read from or to be written to a memory cell array, and an internal controller. The memory controller may transmits a mode signal to the non-volatile memory in response to a control signal, the control signal corresponds to either a read mode or a write mode to be applied to the non-volatile memory. In response to the mode signal, the internal controller may control the data to be read to be stored in the buffer memory, if the read mode is to be applied, and the internal controller may control the buffer memory to stand-by until a write command is received, if the write mode is to be applied.

Abstract: A multi-port volatile memory device can include a first port that is configured for data transfer to/from an external host system and the device. A volatile main memory core is configured to store data received thereat and read requested stored data thereform. A volatile sub memory core can be configured to store data received thereat and read requested stored data therefrom. A main interface circuit can be coupled to the first port and can be configured to provide data to/from the volatile main memory core and the first port in a master mode and can be configured to provide data to/from the volatile sub memory core and the first port in a slave mode. A second port can be configured for data transfer to/from an external non-volatile memory device and the device and a sub interface circuit can be coupled to the second port and configured to provide data to/from the volatile sub memory core and the second port in the slave mode.

Abstract: A multiprocessor system includes first and second processors and a multi-path accessible semiconductor memory device including a shared memory area and a pseudo operation execution unit. The shared memory area is accessible by the first and second processors according to a page open policy. The pseudo operation execution unit responds to a virtual active command from one of the first and second processors to close a last-opened page. The virtual active command is generated with a row address not corresponding to any row of the shared memory area. For example, bit-lines of a last accessed row are pre-charged for closing the last-opened page.

Abstract: A multi-port volatile memory device can include a first port that is configured for data transfer to/from an external host system and the device. A volatile main memory core is configured to store data received thereat and read requested stored data thereform. A volatile sub memory core can be configured to store data received thereat and read requested stored data therefrom. A main interface circuit can be coupled to the first port and can be configured to provide data to/from the volatile main memory core and the first port in a master mode and can be configured to provide data to/from the volatile sub memory core and the first port in a slave mode. A second port can be configured for data transfer to/from an external non-volatile memory device and the device and a sub interface circuit can be coupled to the second port and configured to provide data to/from the volatile sub memory core and the second port in the slave mode.

Abstract: A multipath accessible semiconductor memory device provides an interfacing function between multiple processors which indirectly controls a flash memory. The multipath accessible semiconductor memory device comprises a shared memory area, an internal register and a control unit. The shared memory area is accessed by first and second processors through different ports and is allocated to a portion of a memory cell array. The internal register is located outside the memory cell array and is accessed by the first and second processors. The control unit provides storage of address map data associated with the flash memory outside the shared memory area so that the first processor indirectly accesses the flash memory by using the shared memory area and the internal register even when only the second processor is coupled to the flash memory. The control unit also controls a connection path between the shared memory area and one of the first and second processors.

Abstract: A memory system and related method of operation are disclosed. The memory system includes a memory configured to generate a data strobe signal including “(n/2)+1” clock signals, where “n” is a number of base data blocks in read data synchronously transferred by the memory during a read operation, and a memory controller configured to receive the read data, receive the data strobe signal, delay the data strobe signal to generate a delayed data strobe signal, and synchronously output “n/2” sampled data blocks to a requesting device in relation to the delayed data strobe signal.

Abstract: A multi-port volatile memory device includes a first port configured for data transfer to/from an external host system and the device. A volatile main memory core is configured to store data received thereat and read requested stored data thereform. A volatile sub memory core is configured to store data received thereat and read requested stored data therefrom. A main interface circuit is coupled to the first port and configured to provide data to/from the volatile main memory core and the first port in a master mode and configured to provide data to/from the volatile sub memory core and the first port in a slave mode. A second port is configured for data transfer to/from an external non-volatile memory device and the device. A sub interface circuit is coupled to the second port and configured to provide data to/from the volatile sub memory core and the second port in the slave mode.

Abstract: A multiprocessor system and method thereof are provided.

Abstract: A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.

Abstract: A semiconductor device is provided. The semiconductor device includes a storage part storing an address for weak cells in a nonvolatile state; and a dynamic semiconductor memory device including: a memory cell array having normal cells and the weak cells to be refreshed; and a refresh control part performing a refresh operation for the weak cells, wherein a refresh period for the weak cells is shorter than a refresh period for the normal cells when the address applied in a refresh operation mode coincides with the address stored in the storage part.

Abstract: A multiprocessor system includes a first processor coupled to a first bus, a second processor coupled to a second bus, a first memory coupled to the first bus and the second bus, and a second memory coupled to the second bus. The first processor is configured to access the first memory through the first bus, and the second processor is configured to access the first memory and the second memory through the second bus.

Abstract: A semiconductor memory device includes ports, data line pairs, where each port associated with one of the data line pairs, sets of address lines, where each port associated with one of the sets of address lines, a shared memory region of a memory cell array, where the shared memory region accessible through the ports, an access controller coupled to the ports and configured to generate an access selection signal in response to a plurality of control signals received through the ports, and an access router coupled to the shared memory region, the data line pairs, and the sets of address lines, the access router configured to selectively couple one of the sets of address lines and one of the data line pairs to the shared memory region in response to the access selection signal.

Abstract: A plurality of masters arbitrate for access to a shared memory device, such as a SDRAM (synchronous dynamic random access memory), amongst themselves using software and arbitration interfaces. The masters generate additional commands upon arbitration, such as MRS and PALL commands, for prevention of collision of commands, refresh starvation, and/or a missing pre-charge operation in the shared memory device.

Abstract: A multi-port memory system includes a shared memory bank, multiple command decoders configured to receive refresh commands from multiple processors, and a refresh controller coupled to the shared memory bank and the command decoders, and configured to selectively apply refresh commands from the command decoders to the shared memory bank.

Abstract: A system having a memory device accessible by a plurality of processors is provided. The system includes a memory device, a first processor, and a second processor. The memory device has a first memory array part and a second memory array part. The first processor predominantly accesses the first memory array part of the memory device and selectively accesses the second memory array part of the memory device. The second processor predominantly accesses the second memory array part of the memory device and selectively accesses the first memory array part of the memory device.

Abstract: A semiconductor device includes a memory cell array, including at least one of a plurality of memory cells storing program data received from a flash memory, a row address buffer, which receives a row address signal in response to a first strobe signal, and a column address buffer, which receives a column address signal in response to a second strobe signal. The device further includes a write protection circuit, enabled/disabled in response to a first control signal, the write protection circuit outputting a masking control signal in response to the row address signal, the second strobe signal, and second control signals when enabled, and a column decoder, which decodes the column address signal in response to the masking control signal and enables at least one of a plurality of column selection lines of the memory cell array, corresponding to the decoded column address signal, or disables the column selection lines.

Abstract: A memory system includes a first external device, a second external device, and a multi-port memory device connected to the first and second external devices. The multi-port memory system includes: a first port and a second port connected to the first and second external devices, respectively, a first bank group having at least one memory bank, the first bank group configured to be accessed by the first external device through the first data port; a second bank group having at least one memory bank, the second bank group configured to be accessed by the second external device through the second data port; a third bank group having at least one memory bank, wherein the third bank group is configured to be selectively accessed by the first external device through the first data port or the second external device through the second data port. The multi-port memory system may prevent data collisions which occur when two ports simultaneously attempt to access the same memory bank.