Abstract: A moving picture decoder further includes a plurality of switches in a mesh configuration, and at least one On-Chip Network (OCN) arranged in a star configuration and coupled to the plurality of switches. The On-Chip Network (OCN) includes a plurality of slave modules coupled to the On-Chip Network (OCN) and arranged in a star configuration.

Abstract: A switch block circuit in a field programmable gate array is provided. The switch block circuit includes a configuration memory unit including first group memories and second group memories and a switching unit including first group switching transistors and second group switching transistors. The switch block circuit further includes a selection unit for correspondingly connecting the second group memories with the second group switching transistors depending on an operation mode. The switch block is efficiently reconfigurable depending on the intended use, and configuration memories unused in a specific operation mode may be applied to other purposes.

Abstract: A wireless communications terminal includes: an RF wake-up detection unit detecting a first RF signal including an RF ID for waking up; and a wireless communications unit waking up when the RF ID included in the first RF signal detected by the RF wake-up detection unit matches a pre-set reference ID in a sleep mode.

Abstract: There is provided a low drop-out regulator. The low drop-out regulator includes an amplifier including an odd number of operational amplifiers connected to one another in series, and an output unit including a pass transistor operated by an output from the amplifier and generating an output voltage to be applied to a load, wherein the pass transistor is an N-channel transistor, and the amplifier controls a feedback loop gain between an output terminal of one of the odd number of operational amplifiers and the output unit. The feedback loop gain may be controlled independently from the trans-conductance of the pass transistor, whereby the stable output voltage may be generated, even in the case that the load and the input voltage are changed, and the design parameter may be simplified.

Abstract: Disclosed herein is a pad controlling apparatus controlling current and voltage applied to a pad, the pad controlling apparatus including: a voltage drop unit dropping the voltage applied to the pad; a switching unit connected in parallel with the voltage drop unit; and a control unit comparing a level of the dropped voltage and first reference voltage with each other and turning on the switching unit on when the level of the dropped voltage is larger than the first reference voltage. According to the present invention, even though interrupt occurs from the outside, a chip may be normally operated.

Abstract: There are provided a distributed video coding apparatus and method capable of controlling an encoding rate, the apparatus including: an intra-frame encoder encoding a key frame and outputting a bit stream of the encoded key frame; an encoder rate control (ERC) module calculating a bit rate according to motion complexity of a present Wyner-Ziv (WZ) frame by using a correlation between the motion complexity and the bit rate; and a turbo encoder encoding the present WZ frame by the bit rate calculated at the ERC module and outputting the encoded WZ bit stream.

Abstract: A wireless apparatus having a non-electric power-type wake-up function that operates a wake-up circuit waking-up a microprocessor for communications without power. There is provided a wireless apparatus having a wake-up function, including: a wake-up unit that has a rectifying circuit having elements configured as passive elements and rectifies preset first wireless signals to transmit wake-up signals; and a wireless communications unit that is woken-up by the wake-up signals from the wake-up unit to perform communications using preset second wireless signals, in a sleep mode.

Abstract: A switch apparatus of a Field Programmable Gate Array (FPGA) includes a pass transistor configured to switch and transfer an input signal to a logic cell according to a value of a configuration memory, and a voltage maintaining unit connected between the configuration memory and a gate of the pass transistor and configured to delay a drop of a gate voltage.

Abstract: Disclosed herein is a delay circuit for a low power ring oscillator. The delay circuit includes: a pair of N type transistors that receive first differential input signals Vin1+ and Vin1?; a pair of P type transistors that receive second differential input signals Vin2+ and Vin2?; a differential output terminal that outputs differential output signals Vout+ and Vout? generated from the pair of N type transistors and the pair of P type transistors; an N type detector that supplies a body voltage to the pair of N type transistors; and a P type detector that supplies a body voltage to the pair of P type transistors.

Abstract: Disclosed is a wireless communication apparatus having a self sensing function, which can detect an object by use of a wake-up function without employing a separate sensor. The wireless communication apparatus includes a communication unit wirelessly communicating with a server forming a wireless network, and a wake-up unit waking up the communication unit under the control of the server when the communication unit is in sleep mode, and sensing the presence of an object within a preset communication range according to a reflection signal, which is a signal reflected by the object after being transmitted from the communication unit.

Abstract: Disclosed herein is a delay circuit for a low power ring oscillator. The delay circuit includes: a pair of N type transistors that receive first differential input signals Vin1+ and Vin1?; a pair of P type transistors that receive second differential input signals Vin2+ and Vin2?; a differential output terminal that outputs differential output signals Vout+ and Vout? generated from the pair of N type transistors and the pair of P type transistors; an N type detector that supplies a body voltage to the pair of N type transistors; and a P type detector that supplies a body voltage to the pair of P type transistors.

Abstract: The present invention provides a digital amplitude modulator and polar transmitter using the same. The polar transmitter includes: a polar converter for converting an input signal into an amplitude information signal and a phase information signal, and outputting the converted amplitude and phase information signal; a sigma-delta modulator for receiving a fractional part of the amplitude information signal, and generating a correcting value for an integer part of the amplitude information signal; a phase-modulator for upward-modulating the phase information signal outputted from the polar converter, and outputting carrier waves including the upward-modulated phase information signal; and a digital power amplifier for generating an output signal whose amplitude corresponds to the integer part of the amplitude information signal which is subjected to correction by the correcting value, and outputting combining the output signal with an output value of the phase-modulator to output the combined signal.

Abstract: Disclosed are a configuration memory apparatus and a router system using the same. The configuration memory apparatus includes: a selection unit selecting one of a first external device and a storage unit and receiving data; a register storing input data received from the selection unit; a storage unit storing data received from the register; and an I/O unit controlling transmission and reception of data to and from the register and a second external device.

Abstract: An apparatus for generating a parity bit for turbo decoding, and a MAP (Maximum A Posteriori) apparatus are provided. The apparatus for generating a parity bit for turbo decoding includes: a index converter calculating forward and reverse state matrices with respect to a parity bit by maintaining or changing the relationship between the forward and reverse state matrices with respect to information bits and input symbols according to an encoder state; and a parity calculation unit calculating a parity bit by using the forward and reverse state matrices calculated by the parity state matric calculation unit.

Abstract: There is provided a slave network interface circuit for improving the parallelism of an On-Chip network, including: a MUX for selecting one of a Write Address inputted from the On-Chip network and a Read Address to read data from a slave module, which is inputted from a slave network interface (SNI) controller, in response to the control of the SNI controller and inputs the selected address to the slave module; and the SNI controller for controlling writing and reading data at the slave module and generating a Read Address to store data read from the slave module and to transfer to the On-Chip network.

Abstract: Provided is an apparatus and method for performing intra prediction for an image decoder, in which by use of horizontal/vertical blocks adjacent to image data input from an external device, the intra prediction is performed in parallel with respect to 16×16 luminance component and 4×4 luminance component of the image data and then with respect to chrominance component, thereby maximizing efficiency of system to not only reduce execution time and hardware cost but also increase processing speed.

Abstract: Disclosed is a wireless communication apparatus having a self sensing function, which can detect an object by use of a wake-up function without employing a separate sensor. The wireless communication apparatus includes a communication unit wirelessly communicating with a server forming a wireless network, and a wake-up unit waking up the communication unit under the control of the server when the communication unit is in sleep mode, and sensing the presence of an object within a preset communication range according to a reflection signal, which is a signal reflected by the object after being transmitted from the communication unit.

Abstract: Disclosed is a technique that shifts the position of a motion compensation block by an error of a motion field and then performs motion compensation to estimate a current frame from past and future frames in digital video coding (DVC), thereby enhancing the accuracy of current frame estimation results.

Abstract: An anisotropic diffusion method and apparatus based on the direction of an edge are disclosed. In the anisotropic diffusion apparatus, directional pattern masking is performed to determine the direction of an edge in an image including noise, and values obtained through the directional pattern masking are convoluted to calculate the magnitude of an image. If the calculated magnitude value of the edge is larger than a threshold value, the edge of the image is preserved, while if the calculated magnitude value of the edge is not larger than the threshold value, noise cancellation is strengthened, whereby noise can be effectively canceled (or concealed) while preserving the edge representing the characteristics of the image, and thus, an image of high quality can be obtained.

Abstract: An on-chip network interfacing apparatus and method are provided. The apparatus includes a plurality of on-chip network ports; a switch receiving data from a first on-chip network port of the on-chip network ports and transmitting the received data to a second on-chip network port of the on-chip network ports; and an interface unit interfacing an advanced microcontroller bus architecture (AMBA) signal received from an module, which is designed according to an AMBA on-chip bus protocol, and outputting the interfacing result to the first on-chip network port; and interfacing the on-chip network signal received from the first on-chip network port, and outputting the interfacing result to the module. Accordingly, it is possible to establish communications at increased speeds by interfacing a signal according to the AMBA 2.0 on-chip bus protocol with a signal according to the on-chip network protocol.