Abstract: Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.

Abstract: An apparatus for controlling a resource sharing schedule in a multi-decoding system including a multi-decoder formed of a plurality of resources, the apparatus including: a storage unit storing status information of the resources and information required in controlling the resource sharing schedule; and a controller, when a source resource requests assignment of a target resource, assigning the target resource, outputting information of the target resource to the source resource, and updating statuses of the resources, wherein the apparatus controls the resource sharing schedule while bidirectionally connected to the resources to share the resources between the multi-decoders. Accordingly, it is possible to reduce an overall decoding time and controlling a resource usage schedule.

Abstract: There are provided a distributed video coding apparatus and method capable of controlling an encoding rate, the apparatus including: an intra-frame encoder encoding a key frame and outputting a bit stream of the encoded key frame; an encoder rate control (ERC) module calculating a bit rate according to motion complexity of a present Wyner-Ziv (WZ) frame by using a correlation between the motion complexity and the bit rate; and a turbo encoder encoding the present WZ frame by the bit rate calculated at the ERC module and outputting the encoded WZ bit stream.

Abstract: Provided are a self-controlled functional module, and a control method therefor and a system using the same. The functional module, includes: a data input unit for receiving data; a function process unit for performing a specific function based on input data transmitted through the data input unit; a data output unit for outputting a result processed by the function process unit; and an operation control unit for receiving state information individually from the data input unit and the data output unit and controlling operation start of the function process unit based on state information of the data input unit and the data output unit.

Abstract: Provided is an apparatus for controlling multiple powers which is capable of turning on and off the multiple powers in their priorities for systems or components to be supplied with the multiple powers such as a liquid crystal display (LCD) module. In the apparatus for controlling multiple powers, an on-signal of high level is applied to an input terminal, and an output of a control signal generating unit is sequentially changed to a high level whenever a clock is applied to a clock signal input terminal by one period, so that outputs of the multiple powers are sequentially output. In addition, an off signal of low level is applied to the input terminal, and an output of the control signal generating unit is changed to a low level in a reversal order whenever a clock is applied to the clock signal input terminal by one period, so that outputs of the multiple powers are interrupted in the reversal order.

Abstract: Provided is an On-Chip network (OCN) based moving picture decoder. The moving picture decoder includes: a plurality of switches for providing a parallel data transmission path between a predetermined master module and the other master module, a parallel data transmission path between a predetermined master module and a predetermined slave module, and a parallel data transmission path between a predetermined slave module and the other slave module; and a plurality of On-Chip Networks (OCNs) for providing a local parallel data transmission path between predetermined slave modules and a parallel data transmission path between a slave module in a corresponding area and the switches, wherein a OCN structure of the moving picture decoder globally has a mesh structure with the switches as medium and locally has a star structure with each of the ONCs as medium.

Abstract: There is provided a slave network interface circuit for improving the parallelism of an On-Chip network, including: a MUX for selecting one of a Write Address inputted from the On-Chip network and a Read Address to read data from a slave module, which is inputted from a slave network interface (SNI) controller, in response to the control of the SNI controller and inputs the selected address to the slave module; and the SNI controller for controlling writing and reading data at the slave module and generating a Read Address to store data read from the slave module and to transfer to the On-Chip network.

Abstract: Provided is a communication system for improving utilization of on-chip communication architecture and eliminating waiting of a master to use a bus. The communication system includes: a direct memory access controller handling high-capacity data communication among a memory and peripheral devices; a communication switch connected with the direct memory access controller, transferring a header storing information on a location of a passive circuit and a continuous transfer size, and an initial address from an active circuit to the passive circuit, and sending and receiving data to/from the direct memory access controller; and a memory controller sending and receiving the data and the address to/from the direct memory access controller.

Abstract: Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.

Abstract: In the apparatus and method for separating carrier of multicarrier wireless communication receiver system, each carrier separation is performed after a quantization in a wireless communication receiver system such as a received multicarrier CDMA (Code Division Multiple Access) etc., to thereby reduce the whole number of quantizers and separate multicarrier from a received signal.

Abstract: In an apparatus for a TFCI mapping in a wireless communication mobile station, and a method thereof, the apparatus includes an encoding unit for encoding a TFCI transmitted from a main control unit as a CPU; a TFCI mapping unit for generating necessary control parameter and a TFCI code by using a signal encoded by the encoding unit and a signal transmitted from the CPU; and a CPU for controlling the encoding unit and the mapping unit.

Abstract: The present invention relates to a turbo decoder having a state metric, a calculating method using the turbo decoder and a computer-readable recoding medium for executing a calculation method implemented to the turbo decoder. The turbo decoder includes branch metric calculation unit, state metric calculation unit and log likelihood ratio calculation unit. The present invention may reduce calculation steps by simplifying a conventional turbo decode algorithm, reducing a size of a hardware, which the turbo decoder can be implemented in as an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA). The present invention can be implemented in an error correction in wireless communication system and satellite communication system.

Abstract: The present invention relates to a finite field multiplier used for implementing an encrypting algorithm circuit, thereby minimizing power consumption and circuit area in implementing the finite field multiplier with a LFSR (Linear Feedback Shift Register) structure. The Finite field multiplier of the present invention is an operator performing a modular operation on the multiplication result of two data represented on a polynomial basis in a Galois Field into an irreducible polynomial. The LFSR structure is a serial finite field multiplication structure, and has a merit over an array structure and a hybrid structure in application to systems that are limited in size and power due to its simplicity of circuits and also its capability of being implemented in a small size.

Abstract: A 108-tap 1:4 interpolation FIR filter device for digital mobile telecommunication having a single bit input that employs a look-up table minimum scheme and a pipeline structure in which the size of the entire look-up tables is significantly reduced by dividing four coefficient groups into three parts, respectively, and effectively using the symmetry of the 108-tap filter coefficient and the symmetry within the look-up table.

Abstract: A finite impulse response filter of 1:4 interpolation with 108 taps for outputting filter output data of 8 bits with respect to filter input data of 4 bits includes four shifting and storing unit of 27 bits for unifying bits of filter input data of 4 bits, which is 2's complement to shift and store the bi-unified input data, first selection unit for selecting any one of the input data stored in the four shifting and storing unit of 27 bits, address generating unit for generating addresses of lookup tables corresponding to each of a plurality of filter coefficients groups, first to fourth lookup table groups for generating filter outputs of each filter coefficients group, four accumulating unit for shifting the filter outputs of the filter coefficients groups respectively outputted in parallel from the first to the fourth lookup table groups, and second selection unit for serially converting the outputs from each of the four accumulators in accordance with filter coefficients groups.

Abstract: In the present invention, a reference block data within a current image from which a motion vector will be obtained and corresponding search region data within reproduced previous image are stored in a reference block and a search region data memory, respectively. A motion vector of two pixels unit is performed using the reference block and the search region data stored in the memory, thus resulting in obtained a motion vector of two pixels unit. At this time, the reference block and the search region data are used by performing 2:1 sampling in a horizontal direction and a vertical direction, respectively and the search range is ?7˜+7. The structure of the motion search is consisted of a memory for storing a reference block (8×8) of current images and a memory (24×8) for storing a search region storing reproduced previous images.

Abstract: A modulator for an IMT-2000 synchronous mobile station in a digital telecommunication and modulating method thereof, and more particularly, an OCQPSK modulator using FIR filters, each for performing 1:4 interpolation operations for 4 input data and a modulating method thereof. The orthogonal complex quadrature phase shift keying OCQPSK modulating apparatus uses a 1-bit input FIR filter that includes pseudo noise spreading for bifurcating 1-bit data inputted from input channels and pseudo-spreading the bifurcated 1-bit data, an FIR filter for receiving the 1-bit data and performing a filtering operation for pulse shaping, a gain multiplying block for multiplying filtered data outputted from the FIR filter by a gain for respective channels, and a channel adder block for adding data outputted from the gain multiplying block to output I channel and Q channel signals.

Abstract: Disclosed are a turbo decoder, which applies a base-2 binary LogMAP algorithm in implementing a turbo decoder to thereby reduce the hardware requirement and implement a high-speed turbo decoder, which comprising a split for splitting the sum of two input state metrics into an integral and a decimal part; a comparator for comparing the integral parts of the two state metrics to extract a maximum and a minimum integer; a subtractor for obtaining a difference between the original integral part and the maximum or minimum integer value; a lookup table for calculating the sum of exponential terms of base-2 function in the decimal parts; a shifter for shifting only a decimal part with a smaller integral part by the difference; an adder for adding the decimal part and a decimal part with a larger integral part; a log pre-processing block for applying a base-2 logarithm on the decimal part to thereby obtain a final value for the decimal part; and an adder for adding the maximum integral value and the final value for t

Abstract: A motion estimation apparatus is provided. The motion estimation apparatus includes a demultiplexer which receives a selection flag from a user and current image data, and selectively outputs the current image data using one output terminal selected from a plurality of output terminals by the selection flag, a motion estimator which performs a motion estimation operation on the current image data using one motion estimation algorithm selected from a plurality of motion estimation algorithms depending on the output of the demultiplexer, and outputs a motion vector, and a multiplexer which receives the selection flag and outputs the motion vector in response to the selection flag.

Abstract: The present invention relates to a finite field multiplier used for implementing an encrypting algorithm circuit, thereby minimizing power consumption and circuit area in implementing the finite field multiplier with a LFSR (Linear Feedback Shift Register) structure. The Finite field multiplier of the present invention is an operator performing a modular operation on the multiplication result of two data represented on a polynomial basis in a Galois Field into an irreducible polynomial. The LFSR structure is a serial finite field multiplication structure, and has a merit over an array structure and a hybrid structure in application to systems that are limited in size and power due to its simplicity of circuits and also its capability of being implemented in a small size.