Patents by Inventor Han-Lin Wu

Han-Lin Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230069707
    Abstract: In order to prevent observed long-term energy decay of power amplifiers and correspondingly increase the lifespan of CO2 lasers employing them, a hydrogen-doped mixing gas is supplied from an external pipeline during operation or periodic maintenance in order to effectively remove solid contaminants that build-up over time on a surface of a catalyst disposed within the power amplifier.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Chih-Ping YEN, Yen-Shuo SU, Jui-Pin WU, Chun-Lin CHANG, Han-Lung CHANG, Heng-Hsin LIU
  • Publication number: 20230029820
    Abstract: An image sensor is provided. The image sensor includes a substrate, an isolation structure on the substrate, a photoelectric conversion layer, a transparent electrode layer, an encapsulation layer, a color filter layer, and a micro-lens. The isolation structure is electrically non-conductive and defines a plurality of pixel regions on the substrate. The isolation structure prevents cross-talk of electrical signals among pixels. The photoelectric conversion layer is disposed on the pixel regions defined by the isolation structure. The transparent electrode layer is disposed over the isolation structure and the photoelectric conversion layer. The encapsulation layer is disposed over the transparent electrode layer. The micro-lens is disposed on the color filter layer.
    Type: Application
    Filed: August 2, 2021
    Publication date: February 2, 2023
    Inventors: Wei-Lung TSAI, Shin-Hong KUO, Huang-Jen CHEN, Yu-Chi CHANG, Ching-Chiang WU, Han-Lin WU, Hung-Jen TSAI
  • Patent number: 11569562
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.
    Type: Grant
    Filed: August 20, 2020
    Date of Patent: January 31, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Ping Wang, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Chung-Yi Hsu
  • Publication number: 20220359977
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes: patch antennas, encapsulated by a first encapsulant; a device die, vertically spaced apart from the patch antennas, and electrically coupled to the patch antennas; and at least one redistribution structure, disposed between the patch antennas and the device die, and including electromagnetic bandgap (EBG) structures laterally surrounding each of the patch antennas.
    Type: Application
    Filed: July 27, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Ping Wang, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu, Chung-Yi Hsu
  • Publication number: 20220352333
    Abstract: A thin film transistor includes a gate electrode embedded in an insulating layer that overlies a substrate, a gate dielectric overlying the gate electrode, an active layer comprising a compound semiconductor material and overlying the gate dielectric, and a source electrode and drain electrode contacting end portions of the active layer. The gate dielectric may have thicker portions over interfaces with the insulating layer to suppress hydrogen diffusion therethrough. Additionally or alternatively, a passivation capping dielectric including a dielectric metal oxide material may be interposed between the active layer and a dielectric layer overlying the active layer to suppress hydrogen diffusion therethrough.
    Type: Application
    Filed: November 11, 2021
    Publication date: November 3, 2022
    Inventors: Min-Kun DAI, Wei-Gang CHIU, I-Cheng CHANG, Cheng-Yi WU, Han-Ting TSAI, Tsann LIN, Chung-Te LIN
  • Patent number: 11478966
    Abstract: A composite plate structure includes a composite plate and a resin component. The composite plate includes a first fiber layer, a second fiber layer and a core layer. The second fiber layer has a first region, wherein an area of the second fiber layer is smaller than an area of the first fiber layer. The core layer is disposed between the first fiber layer and the second fiber layer, wherein the core layer is exposed at the first region. The resin component is connected to the composite plate, wherein the resin component is combined with the core layer at the first region. In addition, a manufacturing method of the composite plate is also provided.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: October 25, 2022
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Jung-Chin Wu, Po-An Lin, Sheng-Hung Lee, Han-Ching Huang, Kuo-Nan Ling
  • Publication number: 20220336671
    Abstract: A planar insulating spacer layer is formed over a substrate, and a vertical stack of a gate electrode, a gate dielectric layer, and a first semiconducting metal oxide layer may be formed thereabove. The first semiconducting metal oxide layer includes atoms of a first n-type dopant at a first average dopant concentration. A second semiconducting metal oxide layer is formed over the first semiconducting metal oxide layer. Portions of the second semiconducting metal oxide layer are doped with the second n-type dopant to provide a source-side n-doped region and a drain-side n-doped region that include atoms of the second n-type dopant at a second average dopant concentration that is greater than the first average dopant concentration. Various dopants may be introduced to enhance performance of the thin film transistor.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 20, 2022
    Inventors: Min-Kun Dai, I-Cheng Chang, Cheng-Yi Wu, Han-Ting Tsai, Tsann Lin, Chung-Te Lin, Wei-Gang Chiu
  • Publication number: 20220336385
    Abstract: A package includes a semiconductor package including a semiconductor die and a first insulating encapsulation, a substrate, and a second insulating encapsulation. The first insulating encapsulation encapsulates the semiconductor die. The substrate includes a redistribution circuitry, wherein the substrate is electrically coupled to the semiconductor package through the redistribution circuitry. The second insulating encapsulation is disposed on and partially covers the substrate, wherein the substrate is sandwiched between the semiconductor package and the second insulating encapsulation.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • Publication number: 20220302182
    Abstract: An optical device is provided. The optical device includes a substrate and a plurality of optical structures. The substrate includes a plurality of photoelectric conversion elements. The optical structures are disposed above the substrate. Each optical structure corresponds to one photoelectric conversion element. Each optical structure includes a first portion and a second portion. The first portion has a first glass transition temperature. The second portion has a second glass transition temperature. The second portion guides the incident light into the photoelectric conversion element. The first glass transition temperature is higher than the second glass transition temperature.
    Type: Application
    Filed: December 28, 2021
    Publication date: September 22, 2022
    Inventors: Shin-Hong KUO, Han-Lin WU, Ta-Yung NI, Ching-Chiang WU, Zong-Ru TU, Yu-Chi CHANG, Hung-Jen TSAI
  • Patent number: 11424197
    Abstract: A package includes a semiconductor package including a semiconductor die and a first insulating encapsulation, a substrate, and a second insulating encapsulation. The first insulating encapsulation encapsulates the semiconductor die. The substrate includes a redistribution circuitry, wherein the substrate is electrically coupled to the semiconductor package through the redistribution circuitry. The second insulating encapsulation is disposed on and partially covers the substrate, wherein the substrate is sandwiched between the semiconductor package and the second insulating encapsulation.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • Publication number: 20220254930
    Abstract: A planar insulating spacer layer is formed over a substrate, and a vertical stack of a gate electrode, a gate dielectric layer, and a first semiconducting metal oxide layer may be formed thereabove. The first semiconducting metal oxide layer includes atoms of a first n-type dopant at a first average dopant concentration. A second semiconducting metal oxide layer is formed over the first semiconducting metal oxide layer. Portions of the second semiconducting metal oxide layer are doped with the second n-type dopant to provide a source-side n-doped region and a drain-side n-doped region that include atoms of the second n-type dopant at a second average dopant concentration that is greater than the first average dopant concentration. Various dopants may be introduced to enhance performance of the thin film transistor.
    Type: Application
    Filed: February 11, 2021
    Publication date: August 11, 2022
    Inventors: Min-Kun DAI, I-Cheng CHANG, Cheng-Yi WU, Han-Ting TSAI, Tsann LIN, Chung-Te LIN, Wei-Gang CHIU
  • Publication number: 20220254722
    Abstract: A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure.
    Type: Application
    Filed: April 25, 2022
    Publication date: August 11, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • Patent number: 11404586
    Abstract: A planar insulating spacer layer is formed over a substrate, and a vertical stack of a gate electrode, a gate dielectric layer, and a first semiconducting metal oxide layer may be formed thereabove. The first semiconducting metal oxide layer includes atoms of a first n-type dopant at a first average dopant concentration. A second semiconducting metal oxide layer is formed over the first semiconducting metal oxide layer. Portions of the second semiconducting metal oxide layer are doped with the second n-type dopant to provide a source-side n-doped region and a drain-side n-doped region that include atoms of the second n-type dopant at a second average dopant concentration that is greater than the first average dopant concentration. Various dopants may be introduced to enhance performance of the thin film transistor.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Min-Kun Dai, I-Cheng Chang, Cheng-Yi Wu, Han-Ting Tsai, Tsann Lin, Chung-Te Lin, Wei-Gang Chiu
  • Publication number: 20220173138
    Abstract: A solid-state image sensor is provided. The solid-state image sensor includes a semiconductor substrate having photoelectric conversion elements. The photoelectric conversion elements form an N×N pixel array, where N is a positive integer larger than or equal to 3. The solid-state image sensor also includes a modulation layer disposed above the photoelectric conversion elements. The solid-state image sensor further includes a light-adjusting structure disposed on the modulation layer and corresponding to the N×N pixel array. The N×N pixel array includes a first pixel region having at least one first pixel. The N×N pixel array also includes a second pixel region adjacent to the first pixel region in a first direction and in a second direction different from the first direction and having second pixels. The aperture ratio of the first pixel and the aperture ratio of the second pixel are different.
    Type: Application
    Filed: November 30, 2020
    Publication date: June 2, 2022
    Inventors: Hui-Min YANG, Zong-Ru TU, Yu-Chi CHANG, Han-Lin WU
  • Publication number: 20210288090
    Abstract: A solid-state image sensor is provided. The solid-state image sensor includes a plurality of photoelectric conversion elements. The solid-state image sensor also includes a first color filter layer disposed above the photoelectric conversion elements and having a plurality of first color filter segments. The solid-state image sensor further includes a second color filter layer disposed adjacent to the first color filter layer and having a plurality of second color filter segments. The solid-state image sensor includes a first grid structure disposed between the first color filter layer and the second color filter layer. The first grid structure has a first grid height. The solid-state image sensor also includes a second grid structure disposed between the first color filter segments and between the second color filter segments. The second grid structure has a second grid height that is lower than or equal to the first grid height.
    Type: Application
    Filed: March 10, 2020
    Publication date: September 16, 2021
    Inventors: Ching-Hua LI, Yu-Chi CHANG, Cheng-Hsuan LIN, Han-Lin WU
  • Patent number: 10850462
    Abstract: A method for fabricating an optical element is provided. A substrate is provided. A plurality of metal grids are formed on the substrate. An organic layer is formed on the substrate and the metal grids. The organic layer is etched to form a first patterned organic layer including a plurality of first protrusion portions and a plurality of first trenches surrounded by the first protrusion portions. The first patterned organic layer is etched to form a second patterned organic layer including a plurality of second protrusion portions and a plurality of second trenches surrounded by the second protrusion portions. Each second protrusion portion covers one metal grid. There is a distance between the center axis of one second protrusion portion of the second patterned organic layer and the center axis of one metal grid covered by the one second protrusion portion of the second patterned organic layer.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: December 1, 2020
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Sheng-Chuan Cheng, Hao-Min Chen, Chi-Han Lin, Han-Lin Wu
  • Publication number: 20200254485
    Abstract: An optical element is provided. The optical element includes a substrate; a plurality of metal grids formed on the substrate; an oxide layer formed on the substrate between the plurality of metal grids; and a plurality of organic layers formed on the plurality of metal grids, wherein the width of the organic layer is greater than the width of the metal grid, and there is at least one gap between the organic layer and the oxide layer.
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Inventors: Sheng-Chuan CHENG, Huang-Jen CHEN, Chi-Han LIN, Han-Lin WU
  • Patent number: 10675657
    Abstract: A method for fabricating an optical element is provided. The fabrication method includes the following steps. A substrate is provided. A plurality of metal grids are formed on the substrate. A first organic layer is formed on the substrate between the plurality of metal grids. A second organic layer is formed on the first organic layer and the plurality of metal grids. The second organic layer and the first organic layer are etched to leave the plurality of metal grids and a plurality of patterned second organic layers on the plurality of metal grids. An optical element fabricated by the method is also provided.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: June 9, 2020
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Sheng-Chuan Cheng, Huang-Jen Chen, Chi-Han Lin, Han-Lin Wu
  • Publication number: 20200108573
    Abstract: A method for fabricating an optical element is provided. A substrate is provided. A plurality of metal grids are formed on the substrate. An organic layer is formed on the substrate and the metal grids. The organic layer is etched to form a first patterned organic layer including a plurality of first protrusion portions and a plurality of first trenches surrounded by the first protrusion portions. The first patterned organic layer is etched to form a second patterned organic layer including a plurality of second protrusion portions and a plurality of second trenches surrounded by the second protrusion portions. Each second protrusion portion covers one metal grid. There is a distance between the center axis of one second protrusion portion of the second patterned organic layer and the center axis of one metal grid covered by the one second protrusion portion of the second patterned organic layer.
    Type: Application
    Filed: October 3, 2018
    Publication date: April 9, 2020
    Inventors: Sheng-Chuan CHENG, Hao-Min CHEN, Chi-Han LIN, Han-Lin WU
  • Patent number: D976852
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: January 31, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Sheng-Tsai Wu, Hsin-Han Lin, Yuan-Yin Lo, Kuo-Shu Kao, Tai-Jyun Yu, Han-Lin Wu, Yen-Ting Lin