Abstract: A virtual ground nitride read-only memory array has a matrix of nitride read-only memory cells in which during an erase operation the non-erasing side of nitride read-only memory cells are connected to a common node for enhancing the erase uniformity of the nitride read-only memory array. If an operation requests erasing on the left side of nitride read-only memory cells, a positive voltage is supplied from an internal power supply to the left side for each of the nitride read-only memory cells, and the right side for each of the nitride read-only memory cells is discharged to a common node. The voltage level of the common mode is selected to be sufficiently high in order to prevent from punch through while at the same time sufficiently low to maintain the lateral electric field for erase operation to function optimally.

Abstract: A non-volatile memory package includes a non-volatile memory array having a plurality of transistors that are electrically coupled in series, each of the transistors having an input terminal and an output terminal such that the output terminal of one of the transistors is coupled to the input terminal of a next transistor in a downstream direction. A read voltage supply supplies a voltage to the input terminal of a selected transistor of the plurality of transistors, to induce a cell current between the input terminal and the output terminal of the selected transistor. A bit sensor receives and evaluates a read current from the output terminal of the selected transistor. A shielding voltage applicator applies a voltage to the input terminal or the output terminal of a downstream transistor of the plurality of transistors, the downstream transistor being in the downstream direction from the selected transistor.

Abstract: A serial peripheral flash memory device uses a plurality of dummy input/output terminals to enable the selection of a parallel mode for devices that have a slower serial clock speed. In parallel mode, data is transmitted over the plurality of dummy input/output terminals to allow a plurality of bits to be transmitted at the same time improving the data transmission rate at the slower serial clock speed.

Abstract: A semiconductor device, including a memory cell having a control gate, a source and drain; and a current limiting circuit coupled to the source. The current limiting circuit may be configured to limit a current between the drain and source to not exceed a predetermined value; the current being generated in response to application of first and second voltages to the control gate and drain, respectively. The current limiting circuit may include a transistor comprising a first terminal, a second terminal, and a third terminal, wherein the first terminal may include a source of the transistor, the third terminal may include a drain of the transistor, and the second terminal may include a gate of the transistor, and wherein a stable bias may be applied to the second terminal of the transistor.

Abstract: A non-volatile memory package includes a non-volatile memory array having a plurality of transistors that are electrically coupled in series, each of the transistors having an input terminal and an output terminal such that the output terminal of one of the transistors is coupled to the input terminal of a next transistor in a downstream direction. A read voltage supply supplies a voltage to the input terminal of a selected transistor of the plurality of transistors, to induce a cell current between the input terminal and the output terminal of the selected transistor. A bit sensor receives and evaluates a read current from the output terminal of the selected transistor. A shielding voltage applicator applies a voltage to the input terminal or the output terminal of a downstream transistor of the plurality of transistors, the downstream transistor being in the downstream direction from the selected transistor.

Abstract: In accordance with one embodiment of the invention, a memory device comprises an array of memory cells arranged into word lines and bit lines, with a sense amplifier and a plurality of reference cells for each bit line. The sense amplifier for a bit line compares the output of a memory cell for that bit line with the output of one of the plurality of reference cells for that bit line.

Abstract: The read reference of a nonvolatile memory integrated circuit is changed in response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command.

Abstract: A dual bit flash device comprising a core cell array, each cell of the core cell array is configured to store two bits of data, and a single reference array, each cell of the single reference array comprising a first bit programmed to a low threshold voltage and a second bit programmed to a high threshold voltage.

Abstract: A virtual ground NROM array has a matrix of NROM cells in which during an erase operation the non-erasing side of NROM cells are connected to a common node for enhancing the erase uniformity of the NROM array. If an operation requests erasing on the left side of NROM cells, a positive voltage is supplied from an internal power supply to the left side for each of the NROM cells, and the right side for each of the NROM cells is discharged to a common node. If an operation requests erasing the right side of NROM cells, a positive voltage is supplied from the internal power supply to the right side for each of the NROM cells, and the right side for each of the NROM cells is connected to the common node. The voltage level of the common mode is selected to be sufficiently high in order to prevent from punch through while at the same time sufficiently low to maintain the lateral electric field for erase operation to function optimally.

Abstract: A nitride read only memory (NROM) erase system is disclosed. The NROM erase system comprises at least one memory sector, N sense amplifiers, and N buffers. The memory sector is segmented into N erase retry units according to the number of the sense amplifiers. One buffer corresponds with one erase retry unit and one sense amplifier. The N buffers are used to indicate whether their corresponding erase retry units are erased after an erase process of an erase operation. One of the buffers will be set if its corresponding erase retry unit is not erased. In this case, a subsequent erase process will begin to erase the un-erased erase retry unit. The erase retry units that are erased in a previous erase process will not be affected by the subsequent erase process. A method for using the NROM erase system is also described.

Abstract: A non-volatile memory package includes a non-volatile memory array having a plurality of transistors that are electrically coupled in series, each of the transistors having an input terminal and an output terminal such that the output terminal of one of the transistors is coupled to the input terminal of a next transistor in a downstream direction. A read voltage supply supplies a voltage to the input terminal of a selected transistor of the plurality of transistors, to induce a cell current between the input terminal and the output terminal of the selected transistor. A bit sensor receives and evaluates a read current from the output terminal of the selected transistor. A shielding voltage applicator applies a voltage to the input terminal or the output terminal of a downstream transistor of the plurality of transistors, the downstream transistor being in the downstream direction from the selected transistor.

Abstract: In accordance with one embodiment of the invention, a memory device comprises an array of memory cells arranged into word lines and bit lines, with a sense amplifier and a plurality of reference cells for each bit line. The sense amplifier for a bit line compares the output of a memory cell for that bit line with the output of one of the plurality of reference cells for that bit line.

Abstract: A dual bit flash device comprising a core cell array, each cell of the core cell array is configured to store two bits of data, and a single reference array, each cell of the single reference array comprising a first bit programmed to a low threshold voltage and a second bit programmed to a high threshold voltage.

Abstract: Non-volatile memory circuits according to the present invention provide a reference memory having multiple reference cells that are shared among a group of sense amplifiers through an interconnect conductor line. The higher number of reference cells for each reference memory generates a greater amount of electrical current for charging multiple source lines. The multiple source lines are coupled to the interconnect conductor bar for capacitance matching with a source line coupled to a memory cell in a main memory array. After a silicon wafer out, measurements to the capacitance produced by the source line in the main memory array and the capacitance produced by the source line in the reference array are taken for an optional trimming. A further calibration in capacitance matching is achieved by trimming one of the source lines that is coupled to the interconnect conductor bar and the reference memory, either by cutting a portion of the source line or adding a portion to the source line.

Abstract: A memory cell array, such as an EEPROM flash memory array, includes a current limiting circuit that limits a sum of leakage currents from nonselected memory cells during operation of the array, such as during a programming operation.

Abstract: Non-volatile memory circuits according to the present invention provide a reference memory having multiple reference cells that is shared among a group of sense amplifiers through an interconnect conductor line. The higher number of reference cells for each reference memory generates a greater amount of electrical current for charging multiple source lines. The multiple source lines are coupled to the interconnect conductor bar for capacitance matching with a source line coupled to a memory cell in a main memory array. After a silicon wafer out, measurements to the capacitance produced by the source line in the main memory array and the capacitance produced by the source line in the reference array are taken for an optional trimming. A further calibration in capacitance matching is achieved by trimming one of the source lines that is coupled to the interconnect conductor bar and the reference memory, either by cutting a portion of the source line or adding a portion to the source line.

Abstract: A serial peripheral flash memory device uses a plurality of dummy input/output terminals to enable the selection of a parallel mode for devices that have a slower serial clock speed. In parallel mode, data is transmitted over the plurality of dummy input/output terminals to allow a plurality of bits to be transmitted at the same time improving the data transmission rate at the slower serial clock speed.

Abstract: A nitride read only memory (NROM) erase system is disclosed. The NROM erase system comprises at least one memory sector, N sense amplifiers, and N buffers. The memory sector is segmented into N erase retry units according to the number of the sense amplifiers. One buffer corresponds with one erase retry unit and one sense amplifier. The N buffers are used to indicate whether their corresponding erase retry units are erased after an erase process of an erase operation. One of the buffers will be set if its corresponding erase retry unit is not erased. In this case, a subsequent erase process will begin to erase the un-erased erase retry unit. The erase retry units that are erased in a previous erase process will not be affected by the subsequent erase process. A method for using the NROM erase system is also described.

Abstract: A memory device is disclosed that includes a plurality of word lines and a plurality of memory cells operating in one of a plurality of modes and coupled to at least one of the word lines. The memory device also includes a plurality of reference lines and reference cells. Each reference cell corresponds to one of the operating modes, supplies a reference current for the corresponding mode, and is coupled to at least one of the reference lines. A reference cell current from a reference cell can also be compared to a target range and, if outside the target range, the voltage level on a corresponding referece line can be adjusted accordingly such that the reference current falls within the target range (i.e., reference current trimming).

Abstract: A nitride read only memory (NROM) erase system is disclosed. The NROM erase system comprises at least one memory sector, N sense amplifiers, and N buffers. The memory sector is segmented into N erase retry units according to the number of the sense amplifiers. One buffer corresponds with one erase retry unit and one sense amplifier. The N buffers are used to indicate whether their corresponding erase retry units are erased after an erase process of an erase operation. One of the buffers will be set if its corresponding erase retry unit is not erased. In this case, a subsequent erase process will begin to erase the un-erased erase retry unit. The erase retry units that are erased in a previous erase process will not be affected by the subsequent erase process. A method for using the disclosed NROM erase system is also described.